JP's Website · 2026-05-16 · Finding the Time Part 1 - AArch32

Finding the Time Part 1 - AArch32

Posted on 2026-05-16

Contents

Intro

Kinds of ARM

The Early Years

32-bit Addressing

Application Profile

Real-time Profile

Microcontroller Profile

So what is AArch32?

OK, but about that time thing

Intro

I've recently been spending quite a bit of time working on Rust support for legacy 32-bit ARM architectures. Not in the compiler - that work was done in LLVM long ago, and rustc can just take advantage of it - and not in the standard library - because these are bare metal targets that only use core, and core is largely architecture agnostic.

No, what I've been working on is the run-time library aarch32-rt, and the CPU support library aarch32-cpu. The run-time handles the transition from reset, to running your fn main() written in Rust, and the CPU library provides APIs for things like, turning interrupts on, or reading the System Control Register (SCTLR). On top of that, I've been writing a bunch of examples to check that those crates work correctly. We have examples for:

Programming an ARM Generic Interrupt Controller v3 compatible interrupt controller and handling nested interrupts

Dealing with Undefined Exceptions, Syscalls, Hypercalls and various other kinds of ARM exception

Running code on two processors, with SMP

Running in EL2 (i.e. Hypervisor Mode) on ARM processors that support that

More besides

You can see all the code in the rust-embedded/aarch32 repository on Github.

Kinds of ARM

Just to catch everyone up, it's probably worth a quick note explaining why these crates needed to exist, when Rust already works so well on a variety of ARM systems. Broadly speaking, there are five kinds of ARM system.

The Early Years

The Acorn RISC Machine (ARM) was first introduced in 1985 as a co-processor for the Acorn BBC Microcomputer, using a entirely new 32-bit RISC architecture designed in-house at Acorn. In this design, every instruction was exactly 32-bits in size, meaning that with a 32-bit wide data bus, it could load one complete instruction every time it read from memory. However, the processor only hd a 26-bit address bus. This allowed them to use the unused 8 bits1 in the Program Counter register to hold various processor status flags. This is genius - you can save the PC and the CPSR in a single 32-bit write to memory, but also proved to be a problem once they wanted have use than 64 MiB of address space. But, it was enough for the Acorn Archimedes range of machines, which all shipped with various ARM processors using 26-bit addressing, implementing version 2 of the ARM Architecture.

Incidentally, the ARM Architecture is defined in a documented called the ARM Architecture Reference Manual. Now, as ARM the processor technology was spun out from Acorn into ARM the company, that means this document is officially called the ARM ARM ARM (although I guess now the organisation has a trendy lower-case name and the processor architecture no longer stands for Acorn RISC Machine, it's the arm Arm ARM).

32-bit Addressing

ARM Architecture Version 3 (ARMv3) gave the architecture full 32-bit addressing, at the expense of having to move the CPSR out of the PC, and breaking compatibility with all existing 26-bit applications. The Acorn RiscPC initially shipped with an ARM610 running at 30 MHz, implementing ARMv3, but it mostly ran in 26-bit compatible mode. However if you install RISC OS 4 or newer, or boot Linux, it will run in 32-bit mode.

ARMv4 was the first version of the architecture to be implemented outside of ARM - it was licensed by Digital Equipment Corporation (DEC) to use in their StrongARM processor. At 233 MHz processor was so fast, it was purchased by Acorn for use in the final versions of the Acorn RiscPC. Swapping out a 30 MHz ARM610 for a 233 MHz StrongARM must be quite the speed bump.

A later change to ARMv4, called ARMv4T, introduced a smaller version of the ARM instruction set. It was noted that most instructions didn't need the full 32-bits and, if you were to have an instruction set that only had 16-bit instructions, it would allow you to build an ARM system with a 16-bit wide data bus, making it much cheaper but still keeping the performance acceptable.

The small version of the ARM instruction set is the THUMB instruction set.

Because a thumb is a smaller version of an arm.

What else did you expect from the people who knowingly named a document the ARM ARM ARM?

So, the THUMB instruction set was added in ARMv4T and all ARM processors from then on supported both instruction sets. Indeed, you can switch between instructions sets on a per-function basis - an ARM function can call a THUMB function which can call an ARM function. Because ARM instructions all live at addresses that are a multiple of four2, and all THUMB instructions live at an address that is a multiple of 2, the least significant bit of the Program Counter is always unused told the processor...