Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation

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[2605.12445] Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation

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Computer Science > Performance

arXiv:2605.12445 (cs)

[Submitted on 12 May 2026 (v1), last revised 18 May 2026 (this version, v2)]

Title:Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation

Authors:Ege Beysel, Maximilian Bartel, Jan Moritz Joseph<br>View a PDF of the paper titled Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation, by Ege Beysel and 2 other authors

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Abstract:Scalable vector instruction sets such as Arm SVE enable vector-length-agnostic (VLA) execution, allowing a single implementation to adapt across hardware with different vector lengths. However, they complicate compiler code generation, as tiling and data layout decisions can no longer be fixed at compile time.

We present an approach for enabling VLA code generation in an end-to-end ML compilation pipeline through vector-length-aware packed data layouts and corresponding compiler extensions. We integrate these mechanisms into MLIR/IREE and extend tiling, fusion, and vectorization to operate with scalable vector lengths.

Evaluated on real-world ML workloads on Arm CPUs, our approach generates SVE code that is competitive with, and often outperforms, existing NEON-based code generation within IREE, achieving up to $1.45\times$ speedup. We also outperform PyTorch ecosystem frameworks, including ExecuTorch, TorchInductor, and eager execution, demonstrating the effectiveness of scalable vectorization in a production compiler setting. A simulator-based study further shows that the generated code scales with increasing SVE vector length on compute-bound workloads, supporting performance portability across hardware configurations.

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Performance (cs.PF)

Cite as:<br>arXiv:2605.12445 [cs.PF]

(or<br>arXiv:2605.12445v2 [cs.PF] for this version)

https://doi.org/10.48550/arXiv.2605.12445

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arXiv-issued DOI via DataCite

Submission history<br>From: Jan Moritz Joseph [view email]<br>[v1]<br>Tue, 12 May 2026 17:39:24 UTC (2,131 KB)

[v2]<br>Mon, 18 May 2026 14:35:48 UTC (2,131 KB)

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