[2605.22831] Monte Cimone v3: Where RISC-V Stands in High-Performance Computing

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Computer Science > Distributed, Parallel, and Cluster Computing

arXiv:2605.22831 (cs)

[Submitted on 22 Apr 2026]

Title:Monte Cimone v3: Where RISC-V Stands in High-Performance Computing

Authors:Emanuele Venieri, Simone Manoni, Giacomo Madella, Federico Proverbio, Federico Ficarelli, Luca Benini, Andrea Bartolini<br>View a PDF of the paper titled Monte Cimone v3: Where RISC-V Stands in High-Performance Computing, by Emanuele Venieri and 5 other authors

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Abstract:The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2. We characterize MCv3 using HPL and STREAM benchmarks coupled with power measurements, and compare it against two reference platforms: the Intel Xeon Platinum 8480+(Sapphire Rapids) and the NVIDIA Grace CPU Superchip. Our results show that the SG2044 more than doubles single-core performance and improves scalability compared to SG2042. MCv3 achieves an energy efficiency of 3.08GFLOPs/W which improves of 10x w.r.t. MCv1 and is in the range of x86-64 and Arm servers. On pure performance when normalized on the SIMD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46% performance of Intel Sapphire Rapids server and 91% performance of NVIDIA Grace CPU superchip.

Comments:<br>Extended abstract for RISC-V Summit Europe 2026

Subjects:

Distributed, Parallel, and Cluster Computing (cs.DC)

Cite as:<br>arXiv:2605.22831 [cs.DC]

(or<br>arXiv:2605.22831v1 [cs.DC] for this version)

https://doi.org/10.48550/arXiv.2605.22831

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arXiv-issued DOI via DataCite

Submission history<br>From: Emanuele Venieri [view email]<br>[v1]<br>Wed, 22 Apr 2026 10:59:03 UTC (620 KB)

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