Huawei's 'LogicFolding' chip tech aims to close the gap amid US sanctions

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Huawei's 'LogicFolding' chip tech aims to close the gap amid US sanctions<br>Huawei's chips could reach a transistor density equivalent to a 1.4 nm process node by 2031.

Richard Lai<br>May 25, 2026

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Huawei's semiconductor chief He Tingbo. (Source: Huawei)<br>Huawei has just fired a major shot in the ongoing chip wars — and this time, it isn't about cramming more transistors into smaller geometries. It's about bending time.<br>At the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in Shanghai, Huawei's semiconductor chief He Tingbo unveiled what the company calls the Tau (τ) Scaling Law, along with a new "LogicFolding" chip architecture debuting this fall. The promise: by 2031, Huawei's high-end chips could reach a transistor density equivalent to a 1.4 nm process node — without actually being fabricated on a 1.4 nm process.<br>For Chinese consumers, this matters. Amid ongoing U.S. export controls that restrict China's access to advanced semiconductor technology, Huawei's pitch offers a path to cutting-edge performance without relying on foreign fabs.<br>Instead of chasing Moore's Law through ever-smaller "geometric scaling," Huawei is pitching "time scaling." Tau (τ) is the time constant engineers use to describe how fast signals propagate through circuits. The idea is to redesign everything — transistor structures, wiring, circuit layout, and system architecture — to systematically shrink τ. Shorten signal paths, reduce resistance and parasitic capacitance, and orchestrate data movement smarter, and a chip can behave like a denser, more advanced node even when the underlying process hasn't changed much.<br>The star of the show is LogicFolding. In traditional layouts, logic blocks spread across a mostly flat, two-dimensional plane, with performance increasingly bottlenecked by long, resistive interconnects. LogicFolding "folds" logic to break those layout boundaries, pulling critical paths closer together. That cuts wiring length and load, trims propagation delay, and effectively packs more transistors into a given area.

TSMC-SoIC technology. (Source: TSMC)<br>On paper, this sounds adjacent to what rivals are doing with advanced packaging and 3D structures. TSMC, Intel, and Samsung are pushing gate-all-around FETs, backside power delivery, and 3D stacking schemes like “SoIC,” “Foveros,” and “X-Cube,” respectively. But those approaches still demand leading-edge fabs. Huawei's situation is different: it's process-constrained, leaning largely on SMIC's roughly 7 nm-class nodes — several generations behind the 3 nm and upcoming 2 nm processes feeding Apple, Qualcomm, and AMD. Tau scaling and LogicFolding aren't about marginal gains; they're about survival.<br>For consumers, the geopolitics matter less than what ends up in their hands. Huawei says it has already designed and mass-produced 381 chips over the past six years using this τ-centric approach, spanning phones, PCs, networking, and cloud gear. The Kirin chips launching this fall will be the first smartphone SoCs to fully adopt LogicFolding, with He promising "considerable" performance gains.<br>That dovetails with Huawei's renewed push into halo devices. Its tri-fold Mate XT and follow-up XTs have shown the company can still ship headline-grabbing hardware despite sanctions, with Kirin 9000-series and 9020 chips powering multi-hinge foldables and satellite-messaging flagships like the Pocket 2. The next-gen Kirin, reportedly built on evolved 7 nm tech, is where LogicFolding will need to prove it's more than marketing.

A consumer trying the Huawei Pura X Max foldable phone. (Source: Huawei)<br>The contrast with rivals is stark. Apple, Qualcomm, Samsung, and AMD ride 4 nm/3 nm processes with chiplet designs and 3D-stacked cache, scaling "upwards." Huawei is trying to cheat Moore's Law sideways — folding logic and re-architecting the full stack from device physics to system interconnect around time itself.<br>Big questions remain: how much real-world uplift LogicFolding delivers, how scalable it is across generations, and whether Huawei can manufacture these designs in volume without yield or thermal trouble. Moor Insights & Strategy’s Principal Analyst, Anshel Sag, points out that “none of Huawei's magical chip breakthroughs have actually been scalable,” and that “no way they are just 3 years behind” the competition. But should Huawei deliver, Chinese consumers can look forward to how the next Kirin-powered devices actually feel.

Anshel Sag@anshelsag

None of Huawei's magical chip breakthroughs have actually been scalable. The whole thing with the semiconductor industry is that anything you figure out has to scale to billions of chips; the economics simply don't work out. 14A by 2031 is beyond ambitious, especially considering

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