[2605.24026] A Per-Access Upper Bound for Shared-Resource Interference in Direct-Mapped Multicore Architectures

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Computer Science > Hardware Architecture

arXiv:2605.24026 (cs)

[Submitted on 20 May 2026]

Title:A Per-Access Upper Bound for Shared-Resource Interference in Direct-Mapped Multicore Architectures

Authors:Felipe T. Pedroni<br>View a PDF of the paper titled A Per-Access Upper Bound for Shared-Resource Interference in Direct-Mapped Multicore Architectures, by Felipe T. Pedroni

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Abstract:We present a formal bounding analysis for maximum credible interference in multicore processors under strict architectural invariants: direct-mapped L2 cache (1-way associativity), disabled Miss Status Handling Registers (MSHRs), single-bank main memory, deterministic pinned tasks with fixed physical memory mapping, and a pessimistic L2/memory arbitration policy. We prove that, under these invariants, the per-critical-access stall imposed on a target task T is bounded above by (N-1)Lmem, and that this bound is attained by a synchronized adversarial workload of N-1 congruent-different-tag memory requests issued in phase with T's critical accesses. The argument is per-access and direct, requiring no informal multiplicative interference function. The derivation is purely analytical and discussed in the context of DO-178C/CAST-32A certification objectives for airborne software. Limitations and conditions for applicability are explicitly stated. This work provides a traceable method for separating multicore interference from Worst-Case Execution Time (WCET) budgets under fixed architectural constraints.

Subjects:

Hardware Architecture (cs.AR); Operating Systems (cs.OS); Performance (cs.PF)

ACM classes:<br>C.1.4; B.3; C.3

Cite as:<br>arXiv:2605.24026 [cs.AR]

(or<br>arXiv:2605.24026v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2605.24026

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Felipe Pedroni [view email]<br>[v1]<br>Wed, 20 May 2026 14:07:45 UTC (11 KB)

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