What "Memory Compiler" Actually Means: From Bitcells to GDS Tiling | The Cloudlet

What "Memory Compiler" Actually Means: From Bitcells to GDS Tiling

May 29, 2026 [compiler-design] #memory-compiler #sram #eda #layout-vs-schematic #tiling<br>Most people see the name "memory compiler" and have no idea what it actually does.

1. Compiler Representation

The classical representation is the T-diagram (or Tombstone diagram). It characterizes a compiler by three languages: the source language it reads (A), the target language it emits (B), and the implementation language it is written in (C):

┌───┬───┐<br>│ A → B │<br>└───┴───┘<br>│ C

Read it as: "a program that translates A into B, written in C."

The textbook example is C → machine code. But the definition is broader than that:

Typical compiler: C / C++ → assembly / machine code

The compiler I work on at Synopsys: VHDL / Verilog RTL → simulation / debugging database

Memory compiler : design parameters (depth, width, port…) → all views needed to tape out a chip

Shader compiler: GLSL / HLSL → GPU machine code (e.g., Mesa's NIR pipeline, DXC)

Query compiler: SQL → a physical execution plan (e.g., PostgreSQL's planner/executor)

Bytecode compiler: Java source → JVM bytecode (javac), or JavaScript → V8 bytecode (Ignition)

2. The Raw Material: Inside a Bitcell

The fundamental building block of any SRAM (Static Random-Access Memory) is the bitcell — a tiny circuit that holds one bit. Hardware teams design and characterize these cells by hand; the memory compiler's job is to replicate them at scale.

The most common variant is the 6T bitcell (six transistors). Three signal lines connect it to the outside world: WL (Word Line — selects a row), BL (Bit Line), and BLB (Bit Line Bar, the complementary signal):

WL<br>══════════════════╦══════════════════════════════╦════════<br>║ ║<br>┌─────╫──────────────────────────────╫─────┐<br>│ [ M5 ] [ M6 ] │<br>│ │ │ │<br>BL ──┼─────●───── Q Q' ─────●─────┼── BLB<br>│ │ │ │<br>│ │ ┌───────┐ │ │<br>│ ├─►─┤ INV_R ├───┤ │<br>│ │ │(M2,M4)│ │ │<br>│ │ └───────┘ │ │<br>│ │ │ │<br>│ │ ┌───────┐ │ │<br>│ ├───┤ INV_L ├─◄─┤ │<br>│ │ │(M1,M3)│ │ │<br>│ │ └───────┘ │ │<br>│ │<br>│ bitcell (6T) │<br>└──────────────────────────────────────────┘

Transistor count:

INV_L: PMOS M3 + NMOS M1 = 2

INV_R: PMOS M4 + NMOS M2 = 2

Access transistors: M5, M6 = 2

Total: 6 → "6T"

Positive Feedback: How a Bit Gets Locked

Two inverters connected head-to-tail (cross-coupled ):

Assume Q = 1 (high, Vdd)

INV_R receives 1, outputs 0 to Q'

INV_L receives 0, outputs 1 back to Q

Q stays 1 — a perfect closed loop

This is positive feedback + bistability . As long as Vdd is present, Q and Q' are locked at opposite voltages indefinitely. The stored bit is literally just the voltage sitting on those two nodes. SRAM is called "Static" because — unlike DRAM — it never needs to refresh.

Three Operations

Hold (Standby)

WL = 0, access transistors off

Cross-coupled inverters maintain state entirely on their own; only leakage current flows

Strictly speaking, Hold is a state, not an operation — but datasheets list it alongside Read/Write because designers need leakage current figures for power budgeting

Read

Precharge BL and BLB to Vdd

Assert WL high; M5 and M6 turn on

The side storing 0 pulls its bitline down by ~100 mV

Sense amplifier amplifies the small differential → 1 bit out

Read Disturbance : the moment WL turns on, the high-voltage BLB can pull up Q' (the node storing 0) slightly through M6. If it rises past the switching threshold of INV_L, the cell flips — a Destructive Read . The fix is making the pull-down NMOS M2 stronger (wider) than the access transistor M6. This strength ratio is the Beta Ratio (β = W_pull-down / W_access), typically required to be > 1. This is why the six transistors in a standard bitcell are not all the same size.

Write

Write driver forces BL and BLB to target values (one high, one low)

Assert WL high

Write driver strength overcomes the cell's pull-up → forces the cell to flip

The sizing trade-off between these forces is called the pull-up ratio

Beyond 6T: Other Bitcell Types

6T is not the only option. Different use cases demand different trade-offs:

CellTransistorsKey propertyTypical use<br>6T6High density, standard read/writeL2/L3 caches<br>8T8Isolated read port, no read disturbL1 caches, register files<br>10T10Ultra-low voltage operationNear-threshold designs

The 8T cell adds a dedicated read path (two extra transistors) so the read operation never touches the storage nodes — eliminating read disturbance entirely at the cost of ~33% more area.

3. Why a Memory Compiler Exists

When a hardware team designs an SoC (System on Chip), they need SRAM — lots of it, at many different sizes. The fundamental unit they work with is a cell : the smallest verified building block of an SRAM array. But a chip might need an SRAM of depth 512 × width 32 in one place, and depth 4096 × width 64 in another. Redesigning a new cell from scratch for every configuration is not feasible.

The solution is...