New 3D silicon chip breakthrough could extend Moore’s Law for years | ScienceDaily

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New 3D silicon chip breakthrough could extend Moore’s Law for years

Date:<br>May 30, 2026<br>Source:<br>University of Illinois Grainger College of Engineering<br>Summary:<br>As traditional chip miniaturization slows, researchers have found a way to pack more computing power into the same space by stacking silicon circuits in multiple layers. The new process uses ultra-thin silicon membranes and low-temperature manufacturing techniques to overcome a major obstacle that has long blocked the production of true 3D chips.<br>Share:

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FULL STORY

Scientists may have found the key to the next era of computing: ultra-dense 3D silicon chips built like skyscrapers instead of sprawling suburbs. Credit: Shutterstock

For decades, the computing industry has followed a simple formula: make transistors smaller and pack more of them onto a chip. That strategy fueled the extraordinary rise in computing power predicted by Moore's law. But as components approach atomic scales, engineers are increasingly running into the physical limits of silicon and the effects of quantum mechanics.

Many researchers believe the next major advance will come not from shrinking devices further, but from building upward.

A team led by University of Illinois Grainger College of Engineering materials science and engineering professor Qing Cao has demonstrated a new method for stacking multiple layers of silicon electronics directly on top of one another. The approach could dramatically increase computing density, improve performance, and reduce energy consumption while extending the progress that has driven the semiconductor industry for more than half a century.

"Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It's like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient," Cao explained.

The researchers report that their process achieves device yields of 98‒100% while using standard single-crystalline silicon, the semiconductor material that underpins modern electronics. The results suggest the technique could eventually be adopted by commercial chip manufacturers.

"Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips," Cao said. "For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance."

The findings were published in Nature, a journal that rarely features silicon microelectronics research articles.

Why the Semiconductor Industry Is Looking Upward

For roughly 60 years, Moore's law has guided chip development. The principle predicts that transistor density on integrated circuits will double about every two years, leading to faster and more efficient processors.

That trend has held remarkably well, but it is becoming increasingly difficult to sustain.

"In a sense, we're hitting a limit imposed by physics," Cao said. "If you look at the actual size of transistors, they're not getting smaller, especially in terms of their contacted gate pitch. This is because we're becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we're going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface."

Stacking devices vertically offers an attractive alternative. Instead of continuing to shrink individual transistors, engineers can place multiple layers of circuits on top of one another. This not only creates more room for components but also shortens wiring distances, reducing parasitic capacitance and significantly increasing communication bandwidth between different parts of a chip.

Those advantages are particularly important for artificial intelligence and other data-intensive computing applications.

The Promise of Monolithic 3D Chips

Current commercial 3D chip technologies already use stacking, but they typically involve manufacturing semiconductor devices on separate wafers before bonding them together. Examples include high-bandwidth memory and AMD's 3D V-Cache technology.

While successful, these methods have limitations. Alignment between layers is relatively coarse, and the vertical connections known as through-silicon vias (TSVs) are comparatively large and sparse.

Monolithic three-dimensional integration takes a different...