The State of Open-Source EDA Tools: Breaking Open-EDA for ASIC chip flow
Saad Siddiqui
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The State of Open-Source EDA Tools: Breaking Open-EDA for ASIC chip flow<br>ASIC RTL2GDSII Flow
Saad Siddiqui<br>May 30, 2026
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This series is in continuance with my earlier series of open-source EDA ecosystems, and I’ll delve into the open-source tools required for ASIC digital flow in this article.<br>For most of semiconductor history, chip design has existed behind walls.<br>Thanks for reading! Subscribe for free to receive new posts and support my work.
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Not physical walls, but economic and technological ones.<br>The design of modern ASICs required access to expensive EDA software, proprietary foundry kits, and internal verification infrastructure. This process took decades to mature. The barrier to entry became so high that only governments, large corporations, and a handful of well-funded startups could participate in chip design.<br>Software evolved differently.<br>A student with a laptop could build software using Linux, GCC, Git, and open frameworks. Entire industries emerged because infrastructure became accessible.<br>Hardware never experienced that transition.<br>Until now.<br>Over the last decade, something important has started happening in semiconductor design. Open-source EDA tools have evolved from isolated academic projects into a more connected ecosystem. This ecosystem is now capable of handling large portions of RTL-to-GDSII ASIC flow.<br>But the ecosystem is still immature, the tooling is still fragmented, and many critical signoff-grade capabilities are still missing. But for the first time, open-source ASIC design is no longer hypothetical; there’s an ecosystem you can rely on to design chips on your own.<br>And understanding where it stands today requires understanding the entire ASIC design flow itself.<br>What Does “RTL to GDSII” Actually Mean?
Every chip begins as an idea.<br>That idea eventually becomes millions, sometimes billions of transistors physically manufactured on silicon.<br>The process that transforms hardware behavior into manufacturable geometry is called the RTL-to-GDSII flow.<br>At a simplified level, the flow looks like this:<br>Specs(Specifications) → Micro-architecture → RTL Design → Simulation & Verification → Linting & Static Analysis → Synthesis → Formal Verification → Physical Design → Timing Analysis → DRC/LVS & Physical Verification → GDSII Generation<br>Each stage solves a different engineering problem, uses specialized tooling, and has historically depended almost entirely on proprietary EDA software.<br>Open-source EDA attempts to build alternatives for every part of this pipeline.<br>Some areas have matured surprisingly well.<br>Others remain extremely difficult.<br>1. RTL Design: Describing Hardware Behavior
RTL (Register Transfer Level) is where digital hardware is described using hardware description languages such as Verilog/SystemVerilog or VHDL. Before writing a single line of code, we have the specs(specifications) for how the chip will behave when we have designed it, and then we use the specs to design a micro-architecture, which can be a topic for another day. This article will focus heavily on the tooling required for the RTL2GDSII flow.<br>This is the stage where engineers define:<br>datapaths
pipelines
finite state machines
cache logic
bus interfaces
accelerators
processor behavior etc.
This is all written in VHDL/Verilog/SystemVerilog, which are HDLs(Hardware Description Languages) that are used to describe hardware.<br>In the early days of semiconductor design, engineers manually drew schematics gate by gate. That approach collapsed as transistor counts exploded, by the grace of Moore(Moore’s Law)<br>RTL became the abstraction layer that allowed hardware complexity to scale.<br>Instead of manually connecting gates, engineers could describe behavior:<br>what data moves
when it moves
and how logic reacts to clocks and signals
This changed semiconductor engineering permanently.<br>Open-Source RTL Tools
Verilator: Probably the most successful open-source HDL tool today. Verilator converts synthesizable Verilog/SystemVerilog into optimized C++ models, enabling extremely fast simulation. It is respected not only in academia and startups, but increasingly inside industrial environments as well.
Icarus Verilog(iVerilog): One of the oldest open-source Verilog simulators. Lightweight, accessible, and commonly used for educational and small-scale verification workflows. (I wrote my first Verilog code on this tool!)
PS: There are various other ecosystems for RTL design, but I will be mentioning things that are mostly used by many developers. This does not mean that the other ecosystems are not good enough; mentioning various things here would confuse the readers who are new to this.<br>2. Simulation and Debugging: Does the Design Actually Work?
Writing RTL is only the beginning.<br>Hardware must be verified before fabrication because mistakes in silicon are extremely expensive.<br>Simulation allows...