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The first processor from the European Processor Initiative (EPI) marks another important step towards market readiness. Initial samples of Rhea1 are running in the lab and behaving as expected by the engineers. This is a milestone in the so-called bring-up phase for assessing the processor. Deliveries to customers are scheduled to begin by the end of the year, SiPearl from France announced.

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On May 13, 2026, SiPearl powered on the first Rhea1 processor. The company now estimates another ten weeks for validation of all functions, connections, and performance characteristics. “Initial results are very positive,” writes SiPearl.

In the final Rhea1 version, there are 80 ARM Neoverse V1 standard cores, flanked by 64 GB of High Bandwidth Memory (HBM2e), divided into four memory stacks. Each CPU core integrates two 256-bit vector units (SVE) for parallel computing tasks. Additionally, there are four memory channels for DDR5 RAM and 104 PCI Express 5.0 lanes for expansion cards and controllers.

A Bit of Sovereignty

SiPearl is the most important company in the European processor initiative. The company is tasked with designing high-performance CPUs for European servers, data centers, and supercomputers to reduce the EU's dependence, especially on US companies. However, complete independence is not feasible: manufacturing is handled by the Taiwanese chip contract manufacturer TSMC with its N6 process, an improved version of the 7-nanometer class.

In its announcement, SiPearl does not hold back: customers would appreciate, among other things, “back-door free and kill switch-free security.” It's about digital sovereignty. However, kill switches, which could render processors unusable remotely, have never been discovered in processors from companies like AMD and Intel.

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Niche Existence After Delays

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The first major customer for Rhea1 is the German Jülich Supercomputing Centre (JSC), which plans to install more than 2600 Rhea1 processors in over 1300 server nodes. They will be integrated into an additional CPU module of the Jupiter supercomputer. The complete finished system achieves more than one trillion FP64 computing operations per second (one exaflops), but the Rhea1 CPUs only account for a tiny fraction of this: JSC calculates with a good 5 petaflops, meaning five quadrillion computing operations per second, or 0.005 exaflops.

Rhea1 is unlikely to break out of this niche existence easily. By the end of 2026, the processor will be five years overdue; it was originally supposed to be available in 2021. This is reflected in the specifications: HBM2e is already three generations old, followed by HBM3, HBM3e, and HBM4. Similarly, the 7 nm manufacturing class is almost three generations old. AMD plans to deliver Epyc processors with 2 nm structures this year, including more cores. SiPearl has already begun work on Rhea2 to close the gap.

(mma)

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This article was originally published in

German.

It was translated with technical assistance and editorially reviewed before publication.

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