Pa-RISC Processors from Pa-7000 to Pa-8900

PA-ISC Processors from PA-7000 to PA-8900 – OpenPA.net

OpenPA Hardware Computers Operating Software

PA-RISC Hardware PA-RISC Processors Performance of PA-RISC Precision Architecture PA-RISC Chipsets Buses on PA-RISC HP Graphics adapters SCSI on HP 9000 HP Expansion cards LED codes on HP 9000 Boot menu on HP 9000

PA-RISC Processors

PA-RISC Early PA PA-7000 PA-7100 PA-7100LC PA-7200 PA-7300LC PA-8000 PA-8200 PA-8500 PA-8600 PA-8700 PA-8800 PA-8900

FOCUS PRISM Third Party Hitachi

PA-RISC processors are based on an HP RISC architecture developed in the 1980s, used in HP Unix servers and workstations until the 2000s. There were many different PA-RISC processor incarnations: early 32-bit PA-RISC 1.0 in the 1980s, modern 32-bit PA-RISC 1.1 in the 1990s RISC era and final 64-bit PA-RISC 2.0 until Itanium in the 2000s.

CPU Architecture Year FETs Clock up to Cache max Bus Scalar SMP Units

FOCUS FOCUS 32-bit stack 1982 450k NMOS 18 MHz 16 KB external Custom 1-way yes INT, FPU

TS-1 PA-RISC 1.0 32-bit RISC 1986 TTL 8 MHz 128 KB external Custom 1-way

INT, FPU

NS-1 PA-RISC 1.0 32-bit RISC 1987 144k NMOS 30 MHz 128 KB external SMB 1-way

INT, FPU

PRISM Apollo PRISM 32-bit VLIW 1988

18 MHz 196 KB external X-bus 3-wide yes INT, FPU

NS-2 PA-RISC 1.0 32-bit RISC 1989 183k NMOS 27.5 MHz 1 MB external SMB 1-way yes INT, FPU

PCX PA-RISC 1.0 32-bit RISC 1990 196k 50 MHz 1 MB external SMB 1-way yes INT, FPU

PA-7000 PA-RISC 1.1a 32-bit RISC 1991 577k 66 MHz 512 KB external PBus 1-way

INT, FPU

PA-7100 PA-7150 PA-RISC 1.1b 32-bit RISC 1992 850k 125 MHz 3 MB external PBus 2-way yes INT, FP

PA-7100LC PA-RISC 1.1c 32-bit RISC 1994 900k 100 MHz 1 KB 2 MB L2 GSC 2-way

2 INT, FP MIOC, MAX-1

PA-7200 PA-RISC 1.1d 32-bit RISC 1995 1.3M 140 MHz 2 KB 3 MB L2 Runway 2-way yes 2 INT, FP

PA-7300LC PA-RISC 1.1e 32-bit RISC 1996 9.2M 180 MHz 128 KB 8 MB L2 GSC 2-way

2 INT, FP MIOC, MAX-1

PA-8000 PA-RISC 2.0 64-bit RISC 1996 3.8M 230 MHz 2 MB external Runway 4-way yes 4 INT, 4 FP 2 L/S, MAX-2

PA-8200 PA-RISC 2.0 64-bit RISC 1997 4.5M 300 MHz 4 MB external Runway 4-way yes 4 INT, 4 FP 2 L/S, MAX-2

PA-8500 PA-RISC 2.0 64-bit RISC 1998 140M 440 MHz 1.5 MB on-chip Runway 4-way yes 4 INT, 4 FP 2 L/S, MAX-2

PA-8600 PA-RISC 2.0 64-bit RISC 2000 140M 550 MHz 1.5 MB on-chip Runway 4-way yes 4 INT, 4 FP 2 L/S, MAX-2

PA-8700 PA-RISC 2.0 64-bit RISC 2001 186M 875 MHz 2.25 MB on-chip Runway 4-way yes 4 INT, 4 FP 2 L/S, MAX-2

PA-8800 dual-core PA-RISC 2.0 64-bit RISC 2004 300M 1 GHz 2×1.5 MB 32 MB L2 Itanium 2 2×4-way yes 4 INT, 4 FP 2 L/S, MAX-2 – 2 cores

PA-8900 dual-core PA-RISC 2.0 64-bit RISC 2005 317M 1.1 GHz 2×1.5 MB 64 MB L2 Itanium 2 2×4-way yes 4 INT, 4 FP 2 L/S, MAX-2 – 2 cores

PA-9000 PA-WideWord 64-bit VLIW dropped Explicitly Parallel Instruction Computing (EPIC)

History of PA-RISC

PA-RISC was HP’s RISC architecture, incepted in the 1980s and developed in three versions (PA 1.0, 1.1 and 2.0) in four phases of PA-RISC: Infancy , Growth , Maturity and Decline . Throughout the decades, PA-RISC had strong competition from late CISC and other RISC platforms in the era of technical Unix workstations and business servers.

PA-RISC Infancy Growth Maturity Decline Year 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CPUs 32-bit TS-1 PCX NS-1 NS-2 PA-7000 PA-7100 PA-7100LC PA-7200 PA-7300LC 64-bit PA-8000 PA-8200 PA-8500 PA-8600 PA-8700 PA-8800 PA-8900 Itanium [PA-WideWord] Itanium

Year 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

PA-RISC, the Precision Architecture, was an offspring from HP research and development in the 1980s to replace 16-bit stack-based CPUs in HP 3000 servers and Motorola CPUs in Unix systems with a common, new system architecture, based on new RISC philosophies. PA-RISC platform and ISA were built from the ground up by HP engineers in HP R&D and fabrication facilities.

PA-RISC was implemented almost exclusively in HP’s own processors, built in its VLSI Technology Center (VTC) and Systems & VLSI Technology Operation (SVTO) divisions. PA-RISC started with early TTL and NMOS versions in the 1980s and grew to integrated 32-bit and 64-bit RISC processors in the 1990s and 2000s.

PA-RISC processors started as a conservative RISC design in the 1980s that was developed into a major player of the Unix and RISC era. Performance was on par with other RISCs in the early years, but PA-RISC grew into a high-performance RISC platform in the later 1990s, especially with later PA-8000-based CPUs and competed with supercomputers.

Infancy (early PA-RISC)

First...

Pa-RISC Processors from Pa-7000 to Pa-8900

Related Articles

The Newest Instagram "Exploit" Is the Goofiest I've Seen

It's Not Just X. It's Y

Amazon, Facebook, FBI have access to a private intelligence-sharing network

Show HN: GoPeek – open links in live mini browser windows without new tabs

Agent Memory: An Anatomy