JLink JTAG Access on the Pinecil · Daniel Mangum

It has been more than two years since I bought a Pinecil soldering<br>iron<br>and wrote about soldering the breakout<br>board<br>and accessing the<br>UART.<br>I&rsquo;ve been doing more work with the Pinecil as of late following the addition of<br>upstream support for<br>the Bouffalo Lab BL706<br>MCU in<br>Zephyr (big shout out to<br>@VynDragon,<br>@will-tm, @josuah,<br>and everyone else who has been contributing to the upstream Bouffalo Lab<br>efforts!).

While accessing the UART is helpful for viewing logs, debug access is critical<br>when chasing down early system initialization and driver issues. While there are<br>a variety of JTAG probes on the market, I typically reach for my<br>JLink due to its broad<br>compatibilty and robust tooling. In order to connect a JLink to the Pinecil, the<br>breakout board described<br>in my previous posts is required. It includes a 10-pin header for JTAG breakout<br>with a 3v3 reference pin, 4 GND pins, and the standard JTAG signals. While there<br>are many<br>adapters<br>for attaching various debug pinouts to the JLink 20-pin connector, it is easy<br>to use female-to-female dupont wires to connect the standard 2.54mm pins on the<br>Pinecil breakout and the JLink. The diagram at the top of this post illustrates<br>the pin mapping, and the image below shows the wiring with a ribbon cable<br>between the wires and the JLink (with female-to-male dupont wires), which can be<br>useful to avoid having to reconnect the pins each time if needing to use the<br>JLink for other purposes between Pinecil debugging sessions.

If using a ribbon cable, it can be easy to get confused about orientation when<br>mapping pins. With the notch upwards, the VTref pin (pin 1 on JLink, see<br>white wire below) is in the top left corner of the ribbon cable pinout as it<br>needs to mate with the VTref pin in the top right corner of the JLink<br>pinout.

After connecting, JLinkExe can be used to verify that the mapping is correct.<br>The VTref connection to the breakout board&rsquo;s 3v3 pin should allow the JLink to<br>detect the logic voltage level (~ 3.3V).

JLinkExe

SEGGER J-Link Commander V9.28 (Compiled Mar 18 2026 15:27:55)<br>DLL version V9.28, compiled Mar 18 2026 15:26:49

Connecting to J-Link via USB...O.K.<br>Firmware: J-Link V11 compiled Apr 1 2025 10:02:30<br>Hardware version: V11.00<br>J-Link uptime (since boot): 0d 00h 00m 02s<br>S/N: 821010562<br>License(s): GDB<br>USB speed mode: High speed (480 MBit/s)<br>VTref=3.335V

To attach a debugger, such as gdb, JLinkGDBServer can be used to connect to<br>the JTAG circuitry on the underlying SiFive E24 core<br>complex in the BL706 MCU and<br>start a local gdb server on port 2331.

JLinkGDBServer -device E24 -if JTAG

SEGGER J-Link GDB Server V9.28 Command Line Version

JLinkARM.dll V9.28 (DLL compiled Mar 18 2026 15:26:49)

Command line: -device E24 -if JTAG<br>-----GDB Server start settings-----<br>GDBInit file: none<br>GDB Server Listening port: 2331<br>SWO raw output listening port: 2332<br>Terminal I/O port: 2333<br>Accept remote connection: yes<br>Generate logfile: off<br>Verify download: off<br>Init regs on start: off<br>Silent mode: off<br>Single run mode: off<br>Target connection timeout: 0 ms<br>------J-Link related settings------<br>J-Link Host interface: USB<br>J-Link script: none<br>J-Link settings file: none<br>------Target related settings------<br>Target device: E24<br>Target device parameters: none<br>Target interface: JTAG<br>Target interface speed: 4000kHz<br>Target endian: little

Connecting to J-Link...<br>J-Link is connected.<br>Firmware: J-Link V11 compiled Apr 1 2025 10:02:30<br>Hardware: V11.00<br>S/N: 821010562<br>Feature(s): GDB<br>Checking target voltage...<br>Target voltage: 3.30 V<br>Listening on TCP/IP port 2331<br>Connecting to target...

J-Link found 1 JTAG device, Total IRLen = 5<br>JTAG ID: 0x20000E05 (RISC-V)<br>Halting core...<br>RISC-V RV32 detected. Using RV32 register set for communication with GDB<br>Core implements single precision FPU<br>Connected to target<br>Waiting for GDB connection...

The following gdb command can be used to connect to the server and load the<br>firmware symbols.

gdb -ex 'target remote :2331' ./path/to/firmware.elf

Remote debugging using :2331<br>arch_irq_unlock (key=8) at /home/hasheddan/code/github.com/zephyrproject-rtos/zephyr/include/zephyr/arch/riscv/arch.h:338<br>338 __asm__ volatile ("csrs " RV_STATUS_CSR ", %0"

From there you can start stepping through instructions.

Happy debugging!