Garden of EDA — Open-Source Electronic Design Automation Tools Missing a tool? Open an issue here &rarr;<br>logisim-evolution<br>logisim-evolution<br>Table of contents Features Requirements Downloads Package Manager Nightly builds (unstable) Pictures of Logisim-evolution More Information Bug reports & feature requests For developers How to contribute Credits<br>logisim evolutioneducationcircuit

chisel<br>chipsalliance<br>Chisel: A Modern Hardware Design Language<br>chiselchisel3scala

yosys<br>YosysHQ<br>This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

rocket-chip<br>chipsalliance<br>This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.<br>scalarocket chipchip generator

verilator<br>verilator<br>Verilator open-source SystemVerilog simulator and lint system<br>verilogsystem verilogverilog simulator

iverilog<br>steveicarus<br>1. What is ICARUS Verilog? 2. Building/Installing Icarus Verilog From Source - Compile Time Prerequisites - Compilation - (Optional) Testing - Installation 3. How Icarus Verilog Works - Preprocessing - Parse - Elaboration - Optimization - Code Generation - Attributes 4.

ghdl<br>ghdl<br>This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL).<br>vhdlghdlsimulator

OpenROAD<br>The-OpenROAD-Project<br>OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/<br>opendb databaseopenroadlef

cocotb<br>cocotb<br>cocotb: Python-based chip (RTL) verification<br>pythonvhdlverilog

chipyard<br>ucb-bar<br>An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more<br>rocket chipchip generatorchisel

riscv-boom<br>riscv-boom<br>SonicBOOM: The Berkeley Out-of-Order Machine<br>riscvboomchisel

amaranth<br>amaranth-lang<br>A modern hardware definition language and toolchain based on Python<br>fpgahdlamaranth hdl

SpinalHDL<br>SpinalHDL<br>- A language to describe digital hardware - Compatible with EDA tools, as it generates VHDL/Verilog files - Much more powerful than VHDL, Verilog, and SystemVerilog in its syntax and features - Much less verbose than VHDL, Verilog, and SystemVerilog - Not an HLS, nor based on…<br>scalartlvhdl

verible<br>chipsalliance<br>Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server<br>systemveriloglexeryacc

OpenLane<br>The-OpenROAD-Project<br>OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.<br>asic130nmmagic

nextpnr<br>YosysHQ<br>nextpnr portable FPGA place and route tool

xls<br>google<br>Docs | Quick Start [](https://bit.ly/learn-xls) | Tutorials<br>compilerhigh level synthesishls

fusesoc<br>olofk<br>Package manager and build abstraction tool for FPGA/ASIC development<br>pythonedareuse

wireguard-fpga<br>chili-chips-ba<br>Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!<br>cocotbembeddedfpga

VeriGPU<br>hughperkins<br>OpenSource GPU, in Verilog, loosely based on RISC-V ISA<br>verilogrisc vrisc v assembly

vtr-verilog-to-routing<br>verilog-to-routing<br>Verilog to Routing -- Open Source CAD Flow for FPGA Research<br>vtrfpgacad

abc<br>berkeley-abc<br>ABC: System for Sequential Logic Synthesis and Formal Verification

metroboy<br>aappleby<br>A repository of gate-level simulators and tools for the original Game Boy.<br>veriloggameboygameboy emulator

siliconcompiler<br>siliconcompiler<br>SiliconCompiler is a modular hardware build system ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".<br>asiccmoseda

apio<br>FPGAwars<br>:seedling: Open source ecosystem for open FPGA boards<br>apiocliicestorm

gtkwave<br>gtkwave<br>GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.<br>fstghwvcd

veryl<br>veryl-lang<br>Veryl: A Modern Hardware Description Language<br>rtlrustsystemverilog

nvc<br>nickg<br>NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development.<br>vhdlsimulatorcompiler

vunit<br>VUnit<br>VUnit is a unit testing framework for VHDL/SystemVerilog<br>vhdlverificationsystemverilog hdl

edalize<br>olofk<br>An abstraction library for interfacing EDA tools<br>edafpgafossi

PipelineC<br>JulianKemmerer<br>A C-like hardware description language (HDL) adding...