[2605.13398] FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration

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Computer Science > Hardware Architecture

arXiv:2605.13398 (cs)

[Submitted on 13 May 2026]

Title:FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration

Authors:Shien Zhu, Gustavo Alonso<br>View a PDF of the paper titled FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration, by Shien Zhu and Gustavo Alonso

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Abstract:Online Transaction Processing (OLTP) is a classic application with a growing business. CPU-based OLTP has low lock serving efficiency. The main reason is that most locks are cold, and the lock agent must issue frequent memory accesses to retrieve the lock details to determine whether to grant it. This motivates us to propose dedicated hardware-based lock agents with integrated lock tables to remove the DRAM access overhead.

In this paper, we propose hardware-accelerated lock management and transaction processing for database systems. First, we propose a low-latency lock agent optimized for both lock acquiring and releasing requests. Second, we design a scalable transaction agent that executes the full transaction lifecycle. We present the architecture, optimizations, and design-space exploration of the proposed lock management and transaction processing system. The experiment results show up to 51X higher transaction throughput over the CPU baseline on the TPC-C benchmark.

Comments:<br>10 pages

Subjects:

Hardware Architecture (cs.AR); Databases (cs.DB); Distributed, Parallel, and Cluster Computing (cs.DC)

MSC classes:<br>68M14

ACM classes:<br>C.3

Cite as:<br>arXiv:2605.13398 [cs.AR]

(or<br>arXiv:2605.13398v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2605.13398

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arXiv-issued DOI via DataCite

Submission history<br>From: Shien Zhu [view email]<br>[v1]<br>Wed, 13 May 2026 11:53:59 UTC (2,897 KB)

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