The MilkV Jupiter 2/SpacemiT K3 - Tao of Mac

Rui Carmo

Tao of Mac

Jun 11th 2026 &middot; 22 min read<br>&middot;<br>#ai<br>#hardware<br>#homelab<br>#linux<br>#reviews<br>#riscv<br>#sbc<br>#spacemit

The MilkV Jupiter 2/SpacemiT K3

This is a fascinating box–so much so that after almost three weeks playing with it, I amassed so much material that I nearly decided to split my review into two parts, but in the end I decided to condense it a bit and post a longer piece than usual, even if that means almost half of it is a fairly wide-ranging exploration of how to get AI workloads on it.

The MilkV Jupiter 2 in its metal case

Spoiler: We’re tantalizingly close to having usable non-GPU inference on SBCs, and surprisingly enough, RISC-V is more interesting than ARM right now.

I’ve tested a lot of ARM boards over the past few years, but only a couple of RISC-V machines–and the MilkV Jupiter 2 is quite a substantial system: Sixteen cores (with a twist), a refreshingly roomy 32GB of RAM, a 10GbE SFP, Wi-Fi 6, a GPU with actual DRM nodes, all in a Pico ITX form factor.

Disclaimer: my contacts at Radxa supplied me with a Jupiter 2 free of charge, and as usual, this article follows my review policy.

On paper, this is the first RISC-V board that doesn’t feel like a science project.

In person, and unlike most of the SBCs I get, the Jupiter 2 is a finished product, and came in a neat little box, fully assembled and contained in an unassuming metal case with external antennae as the only extra parts. No power brick, but since it has a USB-C PD port, I had zero trouble powering it from one of my monitors.

Hardware<br>After some careful disassembly, the board itself is pretty dense: 1× DP out, 1× eDP ribbon, 1× USB-C PD power input, 3× USB-A 3.0, 1× GbE RJ-45, 1× 10GbE SFP+ cage, an M.2 slot and what looks like a second M.2 for storage. There are also MIPI/eDP ribbon connectors I haven’t tested.

The board is dwarfed on the top side by the cooler, which I dared not remove

The SoC is SpacemiT’s K3–a big.LITTLE style arrangement with 8×A100 cores at 2GHz and 8×X100 cores at 2.4GHz, which makes it the first RISC-V chip I’ve handled that has asymmetric core clusters. And since there are a few other devices out there with the same reference design, I will henceforth refer to the Jupiter as the K3 for short.

Specs<br>The machine I’m testing has a nice assortment of features:

16 RISC-V cores (8× Spacemit A100 + 8× Spacemit X100)

32GB RAM

128GB UFS

RTL8852BE Wi-Fi 6 + Bluetooth

1 GbE RJ-45 + 10 GbE SFP (RTL8127 10GbE via PCIe)

An IMG (PowerVR) GPU

NOR flash for bootloader (SPI, 8MB: bootinfo + FSBL + env + eSOS + OpenSBI + U-Boot)

PWM fan

Pico ITX form factor

The ISA<br>If you’ve never come across SpacemiT’s stuff before (I had only a bare inkling of the K1), I heartily recommend the public SpacemiT K3 documentation and their GitHub repository since the architecture is laid out there, and it was fairly easy to get a high level grasp. In particular, the K3 SoC datasheet has a pretty good overview:

Block Diagram from the K3 Technical Brief

A key thing that needs to be taken into account is that the A100 cores are fundamentally different from the X100 ones. They have extended vector instruction sets, dedicated transactional memory, and, well… AI.

That documentation also seems to be the original source of the marketing claims that the K3 provides 60 TOPS of AI compute and can run 30B models at over 10 tokens/s. Well, sort of– as another spoiler, I can share that I hit a hard cap at an effective 3B (which seemed to be the practical limit), but we’ll get there…

Hardware Info<br>The board identifies itself as "SpacemiT K3 Pico ITX" in the device tree, and cores are reported like so:

Architecture: riscv64<br>Byte Order: Little Endian<br>CPU(s): 16<br>Vendor ID: 0x710<br>Model name: Spacemit(R) A100<br>Thread(s) per core: 1<br>Core(s) per socket: 8<br>CPU max MHz: 2000.0000<br>CPU min MHz: 614.4000<br>Model name: Spacemit(R) X100<br>Thread(s) per core: 1<br>Core(s) per socket: 8<br>CPU max MHz: 2400.0000<br>CPU min MHz: 614.4000<br>L1d cache: 1 MiB (16 instances)<br>L1i cache: 1 MiB (16 instances)<br>L2 cache: 10 MiB (4 instances)

One of the nice things about this box is that it comes with a 10GbE Realtek NIC. I wasn’t able to test that at full speed yet since my 10GbE interfaces are all in my server closet, but the 802.11ax reported below worked flawlessly with my Wi-Fi 6 setup:

# lspci<br>0000:00:00.0 PCI bridge: SpacemiT X100 PCIe Root Complex (rev 01)<br>0002:00:00.0 PCI bridge: SpacemiT X100 PCIe Root Complex (rev 01)<br>0002:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8127 10GbE Controller (rev 08)<br>0004:00:00.0 PCI bridge: SpacemiT X100 PCIe Root Complex (rev 01)<br>0004:01:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller

There isn’t a lot to report on the USB front (most of the below is what is plugged into my LG Ultrafine):

# lsusb<br>Bus 005 Device 002: ID 043e:9a46 LG Electronics USA, Inc. USB2.1 Hub<br>Bus 005 Device 003: ID...