The Next Computing Revolution May Come From Stacking Chips Like Skyscrapers
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Technology<br>The Next Computing Revolution May Come From Stacking Chips Like Skyscrapers<br>By University of Illinois Grainger College of EngineeringJune 8, 20261 Comment8 Mins Read
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Scientists have demonstrated a breakthrough method for building true 3D silicon chips by stacking multiple layers of circuits without damaging existing electronics. The advance could help extend Moore’s law and deliver faster, more efficient computing as traditional chip scaling reaches its limits. Credit: ShutterstockResearchers may have unlocked the future of computing by turning flat silicon chips into densely stacked 3D architectures.<br>For decades, the semiconductor industry has boosted computing power by making transistors smaller and fitting more of them onto a single chip. That strategy has fueled remarkable advances in electronics, but it is now approaching fundamental physical limits. As devices shrink toward atomic scales, engineers must contend with the constraints of material properties and the effects of quantum mechanics.<br>Researchers believe the next major advance may come not from making chips smaller, but from building them upward.<br>A team at the University of Illinois Grainger College of Engineering has demonstrated a new way to stack layers of silicon circuits directly on top of one another, creating compact three-dimensional chips that could deliver greater computing power while using less energy. Their work, published in Nature, overcomes a major obstacle that has long prevented widespread adoption of this approach.<br>“Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient,” said Qing Cao, a professor of materials science and engineering at Illinois Grainger Engineering.<br>A freestanding sheet of single‑crystalline silicon nanomembrane is held above a silicon wafer patterned with its first layer of electronic circuits. Credit: The Grainger College of Engineering at the University of Illinois Urbana-ChampaignWhy Computer Chips Need a New Direction<br>For more than 60 years, the semiconductor industry has followed Moore’s law, the observation that transistor density on a chip roughly doubles every two years. This trend has served as a guiding target for chip manufacturers, enabling steady gains in performance and efficiency.<br>That progress is becoming increasingly difficult to sustain.<br>“In a sense, we’re hitting a limit imposed by physics,” Cao said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of their contacted gate pitch. This is because we’re becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we’re going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface.”<br>Instead of continuing to shrink transistors, many researchers see vertical integration as the next logical step. Stacking devices in multiple layers creates additional space for circuitry while shortening the wiring needed to connect components. Shorter connections reduce parasitic capacitance and significantly increase communication bandwidth between devices and circuit blocks.<br>These advantages are particularly attractive for artificial intelligence and other data-intensive applications that demand ever-increasing computing performance.<br>Monolithic 3D Chips Offer Major Advantages<br>Several commercial products already use three-dimensional chip technologies. These systems are typically made by manufacturing semiconductor devices on separate wafers and then bonding them together afterward.<br>While that method has enabled technologies such as high-bandwidth memory and 3D V-Cache, it has limitations. The alignment between layers is relatively coarse, and the vertical connections known as through-silicon via (TSV) are comparatively large and widely spaced.<br>Monolithic three-dimensional integration takes a different approach. Instead of stacking completed wafers, each layer is built directly on top of the one beneath it during fabrication.<br>This strategy allows vertical connections to be 10-100 times denser, reduces the distance between layers, and enables alignment with...