Zero ASIC releases Platypus 12nm eFPGA product

Zero ASIC releases Platypus 12nm eFPGA product

Cambridge, MA – Jun 22, 2026 – Zero ASIC, a company on a mission to democratize silicon through chiplets and design automation, today announces general availability of the Platypus Z1015 12nm eFPGA IP core. The Z1015 IP core has already been used by the Zero ASIC chiplet design team to develop a state of the art heterogeneous FPGA chiplet and is now being offered to external customers.

Product Highlights

GF12LPP process node

4.8 mm X 4.8 mm

51K LUTs

63K registers

3Mb BRAM (180x16kbit)

180 DSPs

12K GPIO pins

4 global clocks

APB programming interface

100% open and standardized FPGA architectures

100% open source FPGA bitstream formats

100% open source FPGA development tools

Background

Obsolescence is a critical issue for FPGA-based systems within aerospace, defense, healthcare, communications, automotive, and industrial applications, where lifespans range from 10 to 50 years. This mismatch between the relentless pace of semiconductor advancements and slow infrastructure development cycles has led to an estimated $50B–$70B in obsolescence-related NRE costs for the US military with 15% of all replacement semiconductor parts being counterfeit.

Last year, Zero ASIC made a commitment to “obsolete obsolescence” by launching Platypus, the world’s first open standard FPGA. Platypus Z1015 is released with an open source bitstream, demonstrating our commitment to the promise we made.

Software

Platypus FPGAs are programmable via Logik, a 100% open source suite of development software. Logik is a state of the art automated RTL-to-bitstream toolchain that seamlessly integrates a complete set of industrial strength open source FPGA development tools.

Logik includes support for:

Design languages: SystemVerilog, Verilog, VHDL, C, Chisel, Python, Bluespec

Logic Simulation: Verilator, Icarus, GHDL

Synthesis: Wildebeest

Placement and Routing: VPR

Bitstream Generation: FASM

Build Automation: SiliconCompiler

IP Package Management: SiliconCompiler

To download and install Logik, visit the Logik github repository.

Open architecture and bitstream descriptions for all Platypus devices are located in Logiklib.

Demo

To see just how well Z1015 performs on your code, just pip install and run:

python -m pip install --upgrade logik<br>sc-install -group fpga<br>python your setup.py><br>IP access

To license the Platypus Z1015 IP core or to discuss modifications, contact the Zero ASIC sales team.

About Zero ASIC

Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon through chiplets and design automation. Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.

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