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SystemVerilog

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Hardware description and hardware verification language

SystemVerilogParadigmsStructured (design)<br>Object-oriented (verification)Designed bySynopsys, later IEEEFirst appeared2002; 24 years ago (2002)Stable releaseIEEE 1800-2023<br>/ December 16, 2023; 2 years ago (2023-12-16)

Typing disciplineStatic, weakFilename extensions.sv, .svhInfluenced byVerilog, VHDL, C++ (design)<br>OpenVera, Java (verification)<br>SystemVerilog , standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog.

History<br>[edit]

SystemVerilog started with the donation of the Superlog language to Accellera in 2002 by the startup company Co-Design Automation.[1] The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005.[2] In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009.

The SystemVerilog standard was subsequently updated in 2012,[3] 2017,[4] and most recently in December 2023.[5]

Design features<br>[edit]

The feature-set of SystemVerilog can be divided into two distinct roles:

SystemVerilog for register-transfer level (RTL) design is an extension of Verilog-2005; all features of that language are available in SystemVerilog. Therefore, Verilog is a subset of SystemVerilog.

SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog. These constructs are generally not synthesizable.

The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.

Data lifetime<br>[edit]

There are two types of data lifetime specified in SystemVerilog: static and automatic. Automatic variables are created the moment program execution comes to the scope of the variable. Static variables are created at the start of the program's execution and keep the same value during the entire program's lifespan, unless assigned a new value during execution.

Any variable that is declared inside a task or function without specifying type will be considered automatic. To specify that a variable is static place the "static" keyword in the declaration before the type, e.g., "static int x;". The "automatic" keyword is used in the same way.

New data types<br>[edit]

Enhanced variable types add new capability to Verilog's "reg" type:

logic [31:0] my_var;

Verilog-1995 and -2001 limit reg variables to behavioral statements such as RTL code. SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module. SystemVerilog names this type "logic" to remind users that it has this extra capability and is not a hardware register. The names "logic" and "reg" are interchangeable. A signal with more than one driver (such as a tri-state buffer for general-purpose input/output) needs to be declared a net type such as "wire" so SystemVerilog can resolve the final value.

Multidimensional packed arrays unify and extend Verilog's notion of "registers" and "memories":

logic [1:0][2:0] my_pack[32];

Classical Verilog permitted only one dimension to be declared to the left of the variable name. SystemVerilog permits any number of such "packed" dimensions. A variable of packed array type maps 1:1 onto an integer arithmetic quantity. In the example above, each element of my_pack may be used in expressions as a six-bit integer. The dimensions to the right of the name (32 in this case) are referred to as "unpacked" dimensions. As in Verilog-2001, any number of unpacked dimensions is permitted.

Enumerated data types (enums) allow numeric quantities to be assigned meaningful names. Variables declared to be of enumerated type cannot be assigned to variables of a different enumerated type without casting. This is not true of parameters, which were the preferred implementation technique for enumerated quantities in Verilog-2005:

typedef enum logic [2:0] {<br>RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW<br>} color_t;

color_t my_color = GREEN;<br>initial $display("The color is %s", my_color.name());

As shown above, the designer can specify an underlying arithmetic type (logic [2:0] in this case) which is used to represent the enumeration value. The meta-values X and Z can be used here, possibly to represent illegal states. The built-in function name() returns an ASCII string for the current enumerated value, which is useful in validation and testing.

New integer...