What is IBM’s nanostack chip architecture? - IBM ResearchLearn more about IBM's newest breakthrough, the sub-1 nanometer chip.

Since the advent of microprocessors, semiconductor manufacturers have tried to pack more and more transistors into a given area to boost the performance capabilities of machines. Infinite growth is tricky, though: As transistors have gotten smaller and smaller, we’ve begun to approach the limits of how many can fit onto a chip, requiring creative solutions to these spatial limitations.

Enter the nanostack, a new chip architecture from IBM that makes it possible to build transistors in three dimensions. This innovation represents a paradigm shift. With the nanostack, IBM is unlocking the Z axis for scaling, compared to the past 60-plus years of scaling that have happened in just two dimensions: the X and Y axes. Just as in a high-density cityscape, building upward on a given footprint means more effective square footage. Using this same logic, this new technology unlocks a nearly two times greater number of transistors per unit area over the nanosheet technology IBM used in its 2 nm node chips. Here, IBM researchers figured out how to make 3D devices work by stacking silicon wafers and their constituent transistors on top of each other.

The resulting density is impressive — nearly 100 billion transistors on a chip the size of a fingernail. Initial performance projections show 70% less energy consumption compared to 2nm node chip technologies, as well as 50% speedup over chips using that existing transistor node. This means chips built on nanostack technology would be faster for AI model training and inference, laptop and mobile phone batteries would last longer, and devices could consume less power to achieve the same result.

Announced on Thursday, this breakthrough from IBM is the key to overcoming the existing spatial limitations of microchips to increase transistor density.

What is a nanostack?<br>Why does the world need a new transistor technology?<br>What makes nanostacks difficult?<br>What benefits is nanostack technology unlocking?<br>What innovations are making this possible?<br>What’s next?

What is a nanostack?

Fundamentally, a nanostack is a stack of nanosheets. Nanosheets were developed by IBM and introduced in 2017. They surpassed the dominant fin field-effect transistor (FinFET) technology with gate-all-around (GAA) transistors. This change made it possible to pack transistors more closely without the energy leakage that could happen in such a small space.

But describing the nanostack as just stacked nanosheets belies the true complexity of this new device class. One huge advancement, for example, is that n-type and p-type transistors can be stacked sequentially, rather than being situated side by side. Crucially, separating n- and p-type devices means power and signal can be routed through separate devices.

The two flavors of transistor are built from semiconductor materials that are intentionally “doped” to control how electric current flows. In an n-type transistor, extra electrons are introduced (typically by adding elements like phosphorus to silicon), so negatively charged carriers dominate conduction. In contrast, a p-type transistor is doped with elements like boron that create “holes” (positive charge carriers), allowing current to flow through the movement of these vacancies.

The performance of each type can be enhanced by using different materials. By separating them in a device, IBM is unlocking the possibility to experiment with new materials that optimize the traits of each transistor type, said Nelson Felix, director of technical business development for semiconductors at IBM Research.

Building nanostacks requires new fabrication techniques. The relationship between sheets matters, too. The transistors in nanostacks are situated in alternating arrangements like bricks, rather than one right above the other. Coupled with an extremely tight sub-18-nanometer Back end of line is a stage of semiconductor manufacturing that comes after a wafer is patterned with devices. It describes the network of wires that connect the transistors on a chip.back end of line pitch, nanostacks unlock greater density per unit area.

Why does the world need a new transistor technology?

The simple answer: to overcome some of the challenges that come with transistor density.

“We are running out of tricks to be able to put them closer and closer together, given their different sets of materials,” Felix said.

Intel co-founder Gordon Moore predicted in 1965 that the density of transistors on a chip would double every year. A decade later, though, he revised his prediction, now known as Moore’s Law, to about every two years. It was a subtle acknowledgment and foreshadowing that scaling transistor density brings new challenges.

As an industry, we're running into a fundamental limitation about how closely we can put two different types of transistors together. So instead of building them...