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Home News IBM Outlines Sub-1nm Nanostack Transistor Technology: Building the Next Gen By Going...
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IBM Sub 1nm Node Wafer
More than a few drops of ink have been spilled over the last decade over the death of Moore’s Law. Wherever you stand on just what defines “death” versus merely slowing down, the undeniable fact of the matter is that the overall rate of progress on advancing silicon lithography is slowing down. Compared to the nearly 50-year span of being able to shrink transistors by 50% every two years, in this decade, the pace of change is closer to every five years, and things are even worse for some designs, such as SRAM and analog logic.
The silver (or perhaps, silicon?) lining is that while the pace is slowing down, research into new ways to continue shrinking transistors has ramped up in response. Research teams across the industry are working to discover novel methods of building transistors and materials to build them out of in order to continue the long-standing process of packing ever more transistors into a chip.
To that end, today IBM Research is publicly announcing that they have developed a next-generation transistor design to carry the industry in the next decade, which they are calling the Nanostack. Aimed at sub-1nm geometries – and specifically the 7Å (7 Angstrom) generation – IBM Research believes that the technology can not just carry the torch forward in terms of continuing to shrink transistors, but that nanostack transistors will be the basis of fab node technologies for at least a decade.
The key aspect of the technology is wafer stacking, which is reflected in the “stack” in the name. By stacking parts of a complete logic circuit on top of each other and building up in the vertical direction, IBM believes that the technology will not only unlock the ability to reliably manufacture smaller circuits, but that stacking can be extended to further layers for even greater transistor densities.
A Quick Primer on Transistor Scaling and the Current State of Silicon Lithography
Before getting to the meat of IBM’s announcement, it would likely be helpful to outline the current state of silicon lithography in order to illustrate how IBM’s approach differs from the current generation of technology.
At present, the big three chip fabs, TSMC, Intel, and Samsung, are all in the process of switching from FinFET transistors to Gate All Around (GAAFET) transistors. This is a process that has been years in the making, as FinFET transistors, which have been with the industry since Intel started using them in 2012, have largely run out of headroom. While FinFET transistors were a very effective solution to electron leakage that classic (planar) transistors suffered from at smaller process nodes, modern process nodes are now small enough that not even FinFETs can contain them.
ASML Planar And FinFET Transistor Diagrams<br>The solution to today’s leakage problem, then, is being realized with GAAFET transistors. In effect, an extension of the FinFET idea, a GAAFET transistor places a gate – the part of a transistor that controls...