GitHub - schlae/IBM_MCGA: IBM MCGA reverse engineered chips · GitHub
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IBM_MCGA
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IBM MCGA Gate Array Reverse Engineering
IBM's MCGA (Multi-Color Graphics Array) is a low-cost video chipset introduced<br>with the PS/2 models 25 and 30. The Epson Equity 1e uses MCGA compatible video<br>but does not use the same chips.
The IBM chipset consists of the memory controller gate array and the video<br>formatter gate array. Some examples of these were fabricated on an internal<br>IBM gate array process, while others used an external gate array part by<br>Seiko.
Memory Controller Gate Array (72X8300)
This gate array contains an implementation of the MC6845 sync generator IC,<br>manages the video RAM interface to the ISA bus, manages the character RAM<br>interface, and a few other miscellaneous functions including clock selection<br>and monitor ID readback.
The example I have reverse engineered is implemented using a Seiko SLA6430<br>gate array. It contains 4,342 basic cells (BCs) with 4 transistors each.<br>The BCs are arranged in 167 rows and 26 columns. This is a 2um CMOS process<br>with 2 metal layers.
The image is from 72x8300-sla6430j
The reverse engineered schematic and layout can be found in the mcga72x8300flat<br>subdirectory.
Video Formatter Gate Array (72X8205)
The formatter gate array decodes the ISA memory and IO port addresses,<br>manages the RAMDAC interface, and generates pixel data in both graphics<br>and text modes.
There are two images of this IC. The first,<br>72x8205-gl14105fs<br>appears to be on an internal IBM gate array process. Unfortunately, during<br>decapping, the top metal layer was removed, so the netlist could not be<br>extracted. The second,<br>72x8205-sla6330j, has<br>been reverse engineered: see the mcga72x8205flat subdirectory.
It is a Seiko SLA6330 gate array. It contains 3,312 basic cells with 4<br>transistors each. The BCs are arranged in 144 rows and 23 columns.
72x8300 (Memory Controller Gate Array) Notes
Based on the reverse engineering efforts, new information about MCGA has been<br>discovered.
MCGA can genlock to external HSYNC and VSYNC signals. These signals are<br>brought out to the video connector: pin 12 (ID1) is VSYNC and pin 11 (ID0)<br>is HSYNC. To enable this mode, write a 1 to bit 3 of register 0x12 (character<br>generator interface and sync polarity, or display sense). In the technical reference manual for the PS/2 model 30, this bit is listed as "Reserved = 0".<br>Presumably, this genlock mode would require an external clock PLL connected<br>to the 25MHz or the 14MHz clock input.
Register 0x10 (Mode Control) bit 3, "Compatibility", only affects 80x25 text<br>modes. It causes the horizontal timing registers to be multiplied by 2<br>(and incremented by one, in the case of 0x00, horizontal total, and subtracted by one, in the case of 0x02, start horizontal sync).
Register 0x10 (Mode Control) bit 2, "Clock = 1", controls which clock drives<br>the video circuitry. In the default state, most of the video circuitry uses the<br>25.175MHz clock. You can set clock frequency to the 14.318MHz input by changing<br>this bit to a 0.
Register 0x10 (Mode Control) bit 6, "Reserved = 0", is not yet fully<br>understood.
Register 0x20 (Reserved) is a manufacturing test mode register.
Bit<br>Function
14.318MHz alternate clock mode (unknown)
VCK pin alternate mode (normally VCKIN just goes to VCK)
Speedup mode: unknown
Speedup mode: Cursor position high counter
Speedup mode: Cursor position low/char counter
Speedup mode: Vertical total adjust counter
Speedup mode: Vertical counter
Speedup mode: Horizontal counter
The counter speedup modes basically inject a clock signal into the upper<br>four bits of each counter as well as the lower four bits, so the counter<br>runs out quicker. This is an aid for the factory...