[2606.25313] Programmable Probabilistic Computer with 1,000,000 p-bits

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Computer Science > Distributed, Parallel, and Cluster Computing

arXiv:2606.25313 (cs)

[Submitted on 24 Jun 2026]

Title:Programmable Probabilistic Computer with 1,000,000 p-bits

Authors:Navid Anjum Aadit, Xiuqi Zhang, Shuvro Chowdhury, Kevin Callahan-Coray, Kyle Lee, Saleh Bunaiyan, Sanjay Seshan, Clayton Thomas, Jason Twigg, Andrew Seawright, Forrest Brewer, Tathagata Srimani, Kerem Y. Camsari<br>View a PDF of the paper titled Programmable Probabilistic Computer with 1,000,000 p-bits, by Navid Anjum Aadit and 12 other authors

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Abstract:Probabilistic computers built from p-bits have been proposed as hardware accelerators for sampling and optimizing Ising models, but existing systems have been confined to a single chip, capped by its capacity and memory bandwidth. Here we break this limit by networking FPGAs into a single Ising machine far larger than any one device could hold, realizing a programmable probabilistic computer with one million p-bits. The machine performs Gibbs sampling at over a trillion flips per second while keeping every coupling weight in local on-chip memory. During execution, devices exchange nothing but 1-bit boundary states. This architecture exposes a question fundamental to any distributed sampler: how frequently boundary information must be refreshed for a partitioned machine to behave as an unpartitioned one. Using three-dimensional Edwards-Anderson spin glasses, we show that the answer is set by a single timing ratio, eta = f_comm/f_p-bit, of the boundary-exchange frequency to the local p-bit update frequency. Above a topology-dependent threshold, the distributed machine matches a monolithic GPU reference. Below it, residual energy still decays as a power law but with a reduced exponent, turning parallelism into a quantifiable throughput-accuracy tradeoff. A theoretical cluster mean-field model reproduces the same behavior, showing that this tradeoff is a universal property of partitioned stochastic dynamics. These results provide a programmable million-p-bit platform, demonstrated across spin glasses, Max-Cut, and Boolean satisfiability, together with a quantitative design rule for scaling probabilistic computers beyond the single-chip limit.

Subjects:

Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2606.25313 [cs.DC]

(or<br>arXiv:2606.25313v1 [cs.DC] for this version)

https://doi.org/10.48550/arXiv.2606.25313

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Kerem Çamsarı [view email]<br>[v1]<br>Wed, 24 Jun 2026 02:26:33 UTC (24,044 KB)

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