[2606.31681] Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification

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Computer Science > Cryptography and Security

arXiv:2606.31681 (cs)

[Submitted on 30 Jun 2026]

Title:Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification

Authors:Davis Ranney, Yashaswini I Makaram, A. Adam Ding, Yunsi Fei<br>View a PDF of the paper titled Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification, by Davis Ranney and 3 other authors

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Abstract:As ML-KEM is adopted as a post-quantum cryptographic standard, resilience against physical side-channel attacks has become essential. Among the constituent steps, the decapsulation Fujisaki-Okamoto (FO) verification is particularly vulnerable to side-channel power and electromagnetic (EM) analysis. In this work, we focus on common FPGA-based implementations and examine their side-channel vulnerabilities, and compare them with those of microcontroller implementations. Three verification implementations, unprotected, hash-based (first-order), and higher-order masked, are evaluated for side-channel security on both a microcontroller and an FPGA. While FPGAs offer higher speed and parallelism, they often exhibit stronger side-channel leakage, especially in high bandwidth configurations. The higher-order masked designs still leak information about the underlying data due to hardware-level effects and data-dependent processing. Our experiments show that their parallelized processing on FPGAs introduces sufficient first-order leakage for full secret-key recovery. These results underscore the persistent challenge of securing PQC algorithms in performance-constrained and parallelized hardware environments.

Subjects:

Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2606.31681 [cs.CR]

(or<br>arXiv:2606.31681v1 [cs.CR] for this version)

https://doi.org/10.48550/arXiv.2606.31681

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Davis Ranney [view email]<br>[v1]<br>Tue, 30 Jun 2026 13:57:33 UTC (719 KB)

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