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EDA
IBM 7-Angstrom Tech Squeezes in 100 Billion Transistors<br>The march to ever-smaller transistors continues with IBM’s sub-1-nm technology, which is also stackable.<br>William G. Wong
Related To: Electronic Design
July 1, 2026
2 min read
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What you’ll learn:
What are the challenges with sub-1-nm transistors?
What is the 3D nanostack configuration?
IBM
One of IBM’s sub-1-nm chips holds 100 billion transistors.
We’re down to counting atoms when it comes to IBM’s latest sub-1-nanometer transistor technology (Fig. 1). This technology will initially target high-end AI data centers that have a need for higher-performance systems. The transistors use a gate-all-around or nanosheet approach.
IBM
1. IBM’s latest sub-1 nm transistor technology deals with layers that are only a handful of atoms thick.
Smaller transistors usually mean better performance and greater power efficiency. In this case, the new 7-Å devices bump up performance by 50% while improving power utilization by 70% NanoStackTransistorArchitectureforCMOS7ANodeand_Beyond" target="_blank" rel="noopener">compared to IBM’s 2-nm node.
Designers still have the reticle limit when it comes to production, but making transistors smaller means packing in more within that limit. Packaging technologies like chiplets allow designers to build systems that would not be possible with a single die. Chiplets also make it possible to mix die with different transistor technologies and different functionality like high bandwidth memory (HBM).
3D die stacking has been common with solutions like HBM. However, this technology layers die atop each other. The nanostack does it at the transistor level albeit with only a few levels (Fig. 2). IBM’s research has projected that a 4-track staggered design will deliver a 50% area improvement while reducing power requirements. Both are designed to increase density.
IBM
2. IBM’s sub-1-nm transistors can also be stacked in a 3D nanostack configuration.
IBM’s nanostack configuration is built on a multichannel, nanosheet-on-nanosheet NanoStack CMOS architecture. It employs a vertical inter-FET isolation.
The company’s announcement is about the technology and possibilities rather than release of production devices, but that will come. In the meantime, these announcements highlight how the next generation of electronic devices will be constructed.
About the Author
William G. Wong<br>Senior Content Director - Electronic Design and Microwaves & RF<br>I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a...