[2606.02672] Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow
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arXiv:2606.02672 (cs)
[Submitted on 1 Jun 2026]
Title:Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow
Authors:Corey Lammie<br>View a PDF of the paper titled Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow, by Corey Lammie
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Abstract:Analog In-Memory Computing (AIMC) accelerators execute matrix-vector multiplications directly within memory arrays, reducing data movement and improving DNN inference efficiency. Their limited effective precision motivates heterogeneous architectures that combine analog compute tiles with digital processing units. This letter classifies existing methods for partitioning DNN workloads across these resources by mapping granularity, optimization strategy, and model support, and distills them into a unified four-stage workflow. To demonstrate the workflow on a model class not yet addressed by existing methods, we apply its first two stages to GPT-2, producing the first AIMC-specific precision sensitivity profile for a decoder-only transformer. Sensitivity is dominated by 4 of 49 projections, with the first decoder block's attention output dominating by an order of magnitude. This suggests that projection-level mapping and selective digital execution of early-block and output-facing projections are important for reliable decoder-transformer deployment on AIMC hardware.
Comments:<br>Accepted by IEEE Computer Architecture Letters
Subjects:
Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)
Cite as:<br>arXiv:2606.02672 [cs.AR]
(or<br>arXiv:2606.02672v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2606.02672
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arXiv-issued DOI via DataCite
Journal reference:<br>IEEE Computer Architecture Letters 2026
Related DOI:
https://doi.org/10.1109/LCA.2026.3699929
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DOI(s) linking to related resources
Submission history<br>From: Corey Lammie [view email]<br>[v1]<br>Mon, 1 Jun 2026 12:17:51 UTC (99 KB)
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