Optical Scale Up Fabrics Are Limited By Manufacturing, Not Architecture

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Optical Scale Up Fabrics Are Limited By Manufacturing, Not Architecture

Matt Crowley

Matt<br>Crowley

Published<br>tue 30 Jun 2026 // 14:07 UTC

Earlier this spring, AMD, Broadcom, Meta Platforms, Microsoft, Nvidia, and OpenAI formed the Optical Compute Interconnect Multi-Source Agreement (OCI MSA) to bring coherence to AI infrastructure and establish a specification for co-packaged optics (CPO) scale-up networks. The architecture they aligned on is a slow and wide non-return-to-zero (NRZ) modulation paired with wavelength-division multiplexing. OCI GEN1 supports four wavelengths at 50 Gb/sec per channel, delivering 200 Gb/sec per direction per fiber, and the roadmap scales to 1.6 Tb/sec per fiber per direction.<br>This consortium settled the architectural debate over the direction of networking in AI.

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The specification defines the first step in the architecture, but leaves the harder question open: How bandwidth continues to scale, and what comes after four wavelengths. The roadmap calls for adding wavelengths on the same fiber infrastructure to grow bandwidth, but does not specify which manufacturing approach will deliver them.<br>The Road To More Wavelengths<br>First-movers have already settled this argument. The OCI MSA's founding members endorsed four wavelengths as the GEN1 starting point, Ayar Labs has been on the eight-to-16 wavelength path for years, and Nvidia's published roadmap, "A Roadmap Toward Sub-1 pJ/bit Optical Interconnect," models a 16 wavelength interconnect as the route to the energy targets the MSA aims at.<br>The decision to use slow-and-wide is an energy-per-bit argument. Low symbol rates and simple encoding go together: NRZ carries one bit per symbol, while PAM-4 carries two but requires roughly three times the optical power to hit the same bit-error rate (BER). NRZ holds BER low enough that forward error correction (FEC) stays light, latency remains tight and predictable, and the link stays within its energy budget. On the electrical side, SerDes power per bit at 50 GBaud is roughly one-third that at 100 GBaud.

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That regime must be preserved as bandwidth scales, or it can be walked back. Wavelength multiplication keeps the link inside the slow-and-wide regime, whereas symbol-rate escalation walks the architecture back out of it. For readers who want the underlying physics, see Why 'Optics When You Must' is Now.<br>The industry can now treat increasing wavelength count as settled and turn to the next problem: Manufacturing stable precision laser arrays in massive quantities.<br>Three Eras Of Photonic Integration<br>Photonic integration has evolved through three manufacturing eras. Each was driven by the same forces that drove every transition in the semiconductor industry: Lower cost, higher reliability, and industrial-volume scale.

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The first was the discrete optical assembly era. Components were made separately from exotic materials, precisely aligned by hand, and packaged individually. Expanding system capabilities meant more components and more assembly steps, and every fiber attachment was a costly potential failure point. The cost curve was flat by construction, or even negative, as yields fell.<br>The second era was silicon photonics. Components, including modulators, waveguides, and photodetectors, moved onto a single monolithic wafer, so a portion of the photonic stack could achieve the cost curves of the semiconductor process. Instead of scaling with assembly capacity, the silicon portion could scale by running more wafers on a single flow. The breakthrough was real but incomplete, because critical components could not be integrated. The stubborn, non-silicon III-V gain material was the holdout, and the cost curve remained partial: A high-volume foundry process bolted to a discrete-component bottleneck at the most demanding interface. The foundry flow excluded lasers, semiconductor optical amplifiers (SOA), and high-speed modulators.<br>The third era, heterogeneous integration of all photonic materials on a single wafer, has finally arrived. Combining III-V gain material with silicon photonics brings lasers, semiconductor optical amplifiers, and high-speed modulators into a single wafer-level process. The complete photonics signal chain consolidates on the wafer, and the gain material becomes just another step in a wafer process-flow cost curve, with wafer-level cost, scale, and reliability.<br>The trend towards ever-increasing integration is inevitable. It is the manufacturing transition CMOS underwent in electronics: A single, elegant process that absorbed new device types, compounded over generations at massive scale, and became the foundation for the modern semiconductor industry. Photonics is repeating it, just in time for the massive deployment in AI datacenters.

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The Wavelength Staircase<br>The OCI GEN1...