Neuromorphic Silicon Neuron Controller for Deep Brain Stimulation in Parkinsons

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[2607.05453] Neuromorphic Silicon Neuron Controller for Adaptive Deep Brain Stimulation in Parkinson's Disease

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arXiv:2607.05453 (cs)

[Submitted on 5 Jul 2026]

Title:Neuromorphic Silicon Neuron Controller for Adaptive Deep Brain Stimulation in Parkinson's Disease

Authors:Md Abu Bakr Siddique, Jakub Orłowski, Yan Zhang, Hongyu An<br>View a PDF of the paper titled Neuromorphic Silicon Neuron Controller for Adaptive Deep Brain Stimulation in Parkinson's Disease, by Md Abu Bakr Siddique and 3 other authors

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Abstract:Parkinson's disease (PD) affects millions worldwide and causes severe motor symptoms. Adaptive deep brain stimulation (aDBS) delivers physiologically informed stimulation that can track fluctuations in PD motor symptoms, enabling more intelligent DBS control. However, most existing aDBS approaches are primarily algorithm- and software-driven, with limited efforts toward circuit realization, particularly low-power and implantable integrated circuits. This paper presents the Silicon Leaky Integrate-and-Fire Deep Brain Stimulation (SiLIF-DBS) controller, a neuromorphic silicon neuron stimulator implemented with metal-oxide-semiconductor (CMOS) technology. For system-level evaluation, a simplified computational model of the SiLIF-DBS controller is derived and embedded within a Parkinsonian cortico-basal ganglia framework for closed-loop validation. The system is driven by beta-band subthalamic nucleus local field potentials (STN-LFPs), with their average rectified value (Beta ARV) used as the control biomarker. Our SiLIF-DBS controller for aDBS suppresses pathological beta activity while consuming only 25% of the power required by open-loop stimulation and achieving a suppression efficiency of $5.85\%$/$\mu$W. Overall, our SiLIF-DBS controller achieves strong beta suppression at substantially reduced power, delivering high suppression efficiency that demonstrates it is a viable foundation for low-power implantable aDBS.

Subjects:

Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)

Cite as:<br>arXiv:2607.05453 [cs.AR]

(or<br>arXiv:2607.05453v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2607.05453

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arXiv-issued DOI via DataCite (pending registration)

Related DOI:

https://doi.org/10.1145/3822454.3822465

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Submission history<br>From: Md Abu Bakr Siddique [view email]<br>[v1]<br>Sun, 5 Jul 2026 19:38:23 UTC (2,184 KB)

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