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-- A 4-bit counter: counts up while en is high<br>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.numeric_std.all;
entity pulse_counter is<br>port (<br>clk : in std_logic;<br>rst : in std_logic;<br>en : in std_logic;<br>count : out std_logic_vector(3 downto 0)<br>);<br>end entity pulse_counter;
architecture rtl of pulse_counter is<br>signal count_r : unsigned(3 downto 0);<br>begin
-- One register and one adder: that's the<br>-- whole design once it reaches silicon<br>process (clk) is<br>begin<br>if rising_edge(clk) then<br>if rst = '1' then<br>count_r others => '0');<br>elsif en = '1' then<br>count_r end if;<br>end if;<br>end process;
count std_logic_vector(count_r);
end architecture rtl;
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