Intel Starts Shipping High-NA EUV Silicon
More Than Moore
SubscribeSign in
Intel Starts Shipping High-NA EUV Silicon<br>Coming to a Panther Lake notebook near you!
Dr. Ian Cutress<br>Jul 16, 2026
23
Share
In April 2024 I pulled on a bunny suit at Intel’s D1X fab in Hillsboro, Oregon, and stood a few feet from a machine the size of a bus and worth a small nation state. Intel Fellow Mark Phillips explained this was ASML’s first High-NA EUV scanner, 165 tons of it. Installation had just wrapped and calibration had begun, but realistically still another few months before test wafers could be run. Intel were actually only a few weeks ahead of ASML in terms of installing a tool, enabling a close collaboration between the two.<br>As we toured the tool, about 15 of us or so with CNBC wielding a pre-approved camera setup, the question was if/when this tool was ever going to be involved in production silicon and hardware.<br>The answer landed on July 15, 2026. ASML put out a press release confirming that Intel Foundry has taken High-NA into high-volume manufacturing. Using the tool, Intel is patterning a subset of layers on some of its newest notebook processors: these are Panther Lake, the Core Ultra Series 3 laptop parts built on Intel 18A.<br>From Intel and ASML’s point of view, it means those High-NA layers are dual-qualified in Oregon, and yielding on par with the regular EUV tools that require multiple steps to do the same thing. I asked if this was just test chips, but Intel confirmed it means that notebooks with silicon partly printed on a $380 million High-NA scanner are heading to customers now.<br>Share
Intel Fellow Mark Phillips briefing the group at the High-NA tool in the D1X cleanroom. April 2024. Credit: Intel Corporation<br>Intel has been able to say it owns the world’s first High-NA tool since that 2024 tour, but there has always been a question of using tools like this for research time over production time. Getting product layers through the machine at a yield that matches the mature scanner one bay over is a big step to overcome, the next question is if the economics of a single pass on a more expensive machine work out long term.<br>What the machine actually is
The machine is a two-storey wall of stainless pipework, vacuum vessels and cabling wrapped around a wafer stage, and almost all of it is to serve one number in physics. Every EUV scanner in production until now has imaged through optics with a Numerical Aperture (NA) of 0.33. Numerical aperture describes how wide a cone of light the optics can gather, and a wider cone resolves finer detail, so raising it to 0.55 with High-NA sharpens the smallest single-exposure feature by roughly a third. In practice that lets a fab print in a single cycle a pattern that would need two or three aligned Low-NA exposures stitched together. Each exposure removed takes its cost, its cycle time, and one of its defect opportunities with it - in short, fewer exposures are usually better.
ASML’s first commercial High-NA EUV system at Intel’s D1X Fab<br>Reaching 0.55 was not free, not only with the machine cost but with physics and chip production as well. ASML moved to camera-style anamorphic optics that magnify the mask by different amounts along the two axes - in literal terms this halves the field that the scanner can image in a single shot. Instead of an 858 mm2 chip, or 26 x 33 millimetres, the maximum an EUV machine can do is 429 mm2, or 26 by 16.5 millimeters.<br>A full-reticle die now has to be exposed in two halves and stitched back together, which complicates some of the process simplicity the higher resolution was meant to provide.<br>A single system costs close to $380 million, roughly 2-3 times a Low-NA scanner, and installing one runs to around 250 crates and several months of work on site. Those two facts, a high per-tool cost and a per-exposure penalty set against fewer process steps, have called into question its pricing efficacy.<br>Where High-NA belongs on the roadmap
Where High-NA will do its real work is longer term - as shown by imec’s long term roadmap. On that timeline, 0.33 NA EUV carries the metal-pitch scaling from the N7 era down to about N2, taking pitch from roughly 40 nm to around 21. Compare that to High-NA 0.55 EUV, we extend down to A14 and through to A5 or so. In roadmap terms High-NA is a decade-long tool whose job begins in earnest soon but will carry through into the 2030s.
imec’s Long Range roadmap<br>So why is Intel running it on 18A (its N2 equivalent)? 18A was designed around Low-NA EUV and multi-patterning, and the hardware Intel designed for it does not depend on High-NA to ship. Part of the difficulty of any new technology is ensuring it at least matches what it is replacing, and that’s why the layers on Panther Lake are dual-qualified on both Low-NA and High-NA, rather than just High-NA required. Intel has threaded the machine into a node that would be fine without it, so that by the time 14A/10A arrives and High-NA becomes more of a...