[2607.17899] SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

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arXiv:2607.17899 (cs)

[Submitted on 20 Jul 2026]

Title:SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

Authors:Weiying Wang, Zhiwei Zhang<br>View a PDF of the paper titled SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput, by Weiying Wang and Zhiwei Zhang

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Abstract:Data-parallel workloads in deep learning and scientific computing continue to drive demand for higher processor throughput, energy efficiency, and scalability. The RISC-V Vector Extension (RVV) supports scalable execution through a vector-length-agnostic programming model. However, many tightly coupled implementations still rely on the scalar core to supply vector instructions one at a time, making execution susceptible to vector-instruction supply gaps, scalar-side progression delays, and conservative dependence handling in short-vector, loop-tail, and control/memory-interleaved phases. This paper presents SEAM-V, a hybrid-decoupled vector execution architecture for RVV. SEAM-V forms a continuous stream of execute packets (EPs) through task-level decoupling, local instruction supply, and VLIW-style packing. After an EP is serialized into individual requests, its EP identity and request-bound prefetch context remain visible to the dynamic vector backend, enabling same-EP candidate-hazard suppression and request-bound prefetching. The hybrid-dispatch path can also provide limited cross-EP vector overlap when the required safety conditions are satisfied. Cross-EP dependences, dependences not exempted by the EP contract, resource conflicts, and memory ordering remain dynamically managed by the backend. Cycle-accurate RTL evaluation shows that, compared with an Ara-based tightly coupled RVV implementation (TC), SEAM-V achieves a geometric-mean speedup of 1.34x across 17 representative kernels. The one-dimensional variable-AVL, BLAS and matrix, and fixed-size application groups achieve speedups of 1.50x, 1.25x, and 1.27x, respectively. At AVL=32, the geometric-mean speedup across six one-dimensional vector kernels approaches 3x.

Comments:<br>13 pages, 7 figures, 1 table, and 1 code listing

Subjects:

Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2607.17899 [cs.AR]

(or<br>arXiv:2607.17899v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2607.17899

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Weiying Wang [view email]<br>[v1]<br>Mon, 20 Jul 2026 12:46:50 UTC (350 KB)

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View a PDF of the paper titled SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput, by Weiying Wang and Zhiwei Zhang<br>View PDF<br>HTML (experimental)<br>TeX Source

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