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Home Server Server CPUs Normalizing NVIDIA Vera Benchmarks to AMD EPYC Turin A Framework
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AMD EPYC Turin And NVIDIA Vera
We now have the first benchmarks for the NVIDIA Vera CPUs, as the company released its architectural paper with them. Ryan covered the release in Diving Deeper on NVIDIA’s Vera CPU: New Architectural Details and SPEC CPU 2026 Benchmarks. From the figures released so far, NVIDIA Vera appears to be an interesting Arm-compatible server CPU with its custom Olympus cores. It took a few minutes after NVIDIA published, and then I started fielding questions like how NVIDIA’s multiples of the AMD EPYC speed. Like virtually every company that produces products, NVIDIA crafted favorable comparisons. I wanted to provide a more normalized framework for the Vera to Turin comparison so folks who have not been doing this for a decade and a half or more can have a sense of where we would expect Vera and Turin to fall on a more normalized basis.
A few quick disclosures that we work with both AMD and NVIDIA. Also, we published a more extensive version of the below on our paid Substack earlier, aimed at a different audience.
Helping Normalize NVIDIA Vera to AMD EPYC by Patrick Kennedy
This is a hotly requested topic, so we help cut through the framing
Read on Substack
I still wanted to provide a framework to our STH readers since we have attempted to provide a more balanced view over the years.
Normalizing the NVIDIA Vera Whitepaper Numbers to AMD EPYC Turin
Since NVIDIA dropped its Vera whitepaper just before AMD’s Advancing AI 2026, where we expect to learn more about AMD’s next-generation "Venice" CPU. Companies typically do this because the valid comparison is versus the outgoing generation rather than the concurrent generation. Since we are still under embargo for AMD’s Venice, I wanted to provide a framework to help our readers create a useful comparison framework for NVIDIA’s Vera results. The key points I want to cover are:
Socket and per-core memory bandwidth gains
Core-to-Core Latency, Chiplet Construction, and Glue
Important Cores and SMT Threads
Then we will have a big discussion on normalizing the SPEC CPU2026 performance, and a framework for evaluating AMD EPYC Turin versus NVIDIA Vera through a fairer lens.
These are all framing techniques we have seen in the industry before, so this may not be ground-breaking for many STH readers. At the same time, we want to help folks get more context about what was presented, why, and how to get to an alternate comparison point.
Socket memory bandwidth and per-core memory bandwidth
Memory bandwidth is mostly simple math. It is the number of channels per socket multiplied by the speed of those channels, and faster memory arrives over time. That means a large portion of any bandwidth comparison between CPUs from different years is really a comparison of memory vintages. Twelve channels of DDR5-6400 on the 2024-era EPYC 9755 deliver roughly 0.6TB/s of peak bandwidth. Vera’s LPDDR5X-9600 is up to 1.2TB/s. AMD has already said Venice is 1.6TB/s of memory bandwidth, and we have already...