High Bandwidth Flash (HBF) Overview

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High Bandwidth Flash (HBF) Overview

Updated 12 January 2026

HBF is a NAND flash architecture that uses die stacking, TSVs, and DDR synchronous signaling to deliver terabyte-scale capacity with high-bandwidth performance.

It achieves up to 800 GB/s aggregate bandwidth and 1.6 TiB capacity through advanced techniques like multi-channel/way interleaving and HBM-style host interfaces.

Designed for read-oriented workloads in LLM inference and high-performance accelerators, HBF balances energy efficiency, cost, and thermal management.

High Bandwidth Flash (HBF) is a class of NAND flash memory interface and packaging architectures designed to deliver dramatically higher bandwidth per package—comparable to or exceeding high-bandwidth memory (HBM)—while maintaining the terabyte-scale capacity and cost structure of NAND flash. HBF addresses the critical bottlenecks of bandwidth and capacity in memory-bound applications, most notably in the inference phase of LLMs and high-performance, data-intensive accelerators. Key proposals in this domain leverage die-stacked NAND, double-data-rate synchronous signaling, and controller integration techniques to achieve these ends, with further enhancements via multi-channel/way interleaving, near-memory processing, and direct on-die acceleration.

1. Architectural Principles of High Bandwidth Flash

HBF’s fundamental organizational principles draw from the high-bandwidth die stacking and parallel interface designs of HBM and adapt them for the non-volatile, page-oriented nature of modern NAND flash.

Die Stacking and TSVs (Through-Silicon Vias): HBF packages comprise multiple 3D-NAND dies vertically stacked, each die connected to a controller base die via TSVs. The base die, fabricated in a logic process, embeds all per-channel controllers, error correction (ECC), wear-leveling engines, and PHY circuitry for high-speed parallel transfer (Ma et al., 8 Jan 2026).

HBM-Style Host Interface: The package exposes hundreds to thousands of pins, supporting multi-Gb/s signaling per pin. The PHY and pinout mirror those of HBM, enabling direct connection to existing HBM controllers on accelerators or the adoption of variants via CXL or PCIe (Ma et al., 8 Jan 2026).

DDR Synchronous Flash I/O: At the die and channel level, high-bandwidth signaling is achieved via double-data-rate (DDR) synchronous interfaces. All data transfers occur on both rising and falling edges of a Data Valid Strobe (DVS) signal, coordinated by an on-chip delay-locked loop (DLL). This architecture keeps unchanged the conventional flash pinout, ensuring backward and footprint compatibility (Chung et al., 2015).

Way and Channel Interleaving: Controllers support multiplexing over “ways” (parallel access to multiple flash chips per channel) and multi-channel striping (separate parallel buses), scaling aggregate bandwidth to saturate the host interface (Chung et al., 2015).

2. Quantitative Performance Metrics and Design Equations

HBF architectures are characterized by the following quantitative metrics:

Capacity: A typical HBF stack achieves ~1.6 TiB capacity, an order of magnitude larger than HBM4 (~100 GiB per stack) (Ma et al., 8 Jan 2026).

Bandwidth: Aggregate per-stack bandwidth is targeted at 400–800 GB/s, with Chung et al., 2015).

Power Efficiency: Per-stack power consumption is in the 20–80 W range, corresponding to bandwidth-per-watt >6.4 GB/s/W and capacity-per-watt >6 GiB/W (Ma et al., 8 Jan 2026).

Latency & Granularity: Typical random read latency is 10 µs (compared to DRAM’s 10–100 ns) with transfer granularity at the page level (tens of kB per access) (Ma et al., 8 Jan 2026).

Key equations:

Per-channel bandwidth BW=Bus_width×(edges_per_cycle)/tPBW = \text{Bus\_width} \times (\text{edges\_per\_cycle}) / t_PBW=Bus_width×(edges_per_cycle)/tP​

Stack bandwidth Bstack≃Ndies×BWper_channelB_{stack} \simeq N_{dies} \times...