Nvidia Accelerates Chip Engineering With AI Agents

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Nvidia Accelerates Chip Engineering With AI Agents

Jeff Burt

Jeff<br>Burt

Published<br>mon 27 Jul 2026 // 19:04 UTC

More than a decade ago, Nvidia turned its full focus on artificial intelligence, and since then has been churning out GPUs – and now CPUs – and other hardware designed to power AI systems as well as a wealth of software libraries through CUDA-X and a family of AI models with under the Nemotron umbrella. This has put Nvidia in a leadership role in a rapidly expanding AI industry that has taken over enterprise and HPC datacenter development and made the company extraordinarily wealthy.<br>Part of what drives that wealth is the fact that silicon engineering for AI is increasingly complex with every generation, with demand not only for more chips but also more capabilities, a situation that is pushing the industry beyond what traditional methods can handle. Tim Costa, vice president and general manager of computational engineering at Nvidia, put it in terms that go beyond simply scaling to meet demand.

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Speaking with journalists in a video call, Costa noted that by 2030 the industry is expected to produce 2 trillion chips and process about 41 million wafers a month. In addition, individual packages are approaching a trillion transistors while entire computing systems are on their way to transistor counts that will reach into the quadrillions. At the same time, bringing a chip to market can take years as engineers spend years on the simulation, verification, and implementation steps. That’s a lifetime in the accelerated age of AI.<br>Complexity Outpaces Tradition Chip Design<br>“The key point is not any one number; it's the interaction of scale, architecture, packaging, and system complexity,” he said. “The traditional design process just can't keep pace with that scale of challenge. To meet it, AI and accelerated computing are moving from productivity tools into being foundational engineering infrastructure.”<br>This is where Nvidia and other chip engineering firms are turning to AI.

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“This complexity is compounded by the coupled end-to-end nature of semiconductor innovation,” Costa said. “Decisions in chip architecture affect atomic-scale manufacturing, advanced packaging power, thermals, and the behavior of the complete system. AI helps engineers explore far more design alternatives and make better decisions across those interactions. Accelerated computing makes the high-fidelity simulation, validation, and optimization behind those decisions fast enough to repeat.”<br>Rather than replacing physics or design rules, bringing AI into the chip development process lets engineers put such checks into the loop and use them more often, he explained, adding “the opportunity is to accelerate the full engineering loop, not isolated tools.”<br>Nvidia also is expanding its Agent Toolkit to include updated CUDA-X and PhysicsNeMo libraries for training and deploying engineering AI.<br>In addition, the vendor is working with chip engineering firms Cadence and Synopsys in using its Arm-based “Vera” CV100 CPU (below) to accelerate future generations of its CPUs and GPUs.

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Vera holds 88 custom “Olympus” CPU cores designed by Nvidia and a 1.2 TB/sec LPDDR5X memory subsystem. The company’s second-generation Scalable Coherency Fabric mesh interconnect for strong per-core performance, high memory bandwidth, and low latency for engineering applications, according to Nvidia.

“Nvidia is deploying Vera across the EDA [electronic design automation] workflows used to create our future CPUs and GPUs, including simulation, formal verification, and physical implementation,” Costa said, noting that early engineering testing shows Vera running on Synopsys’ VCS and Cadence’s Jasper platforms provide 1.5 times the performance of AMD’s Epyc Torrent systems. “Its practical value is shorter simulation verification runs. Engineering teams can iterate faster. We are working with Cadence and Synopsys to optimize leading EVA applications for Vera by putting Vera to work helping design Rosa.”<br>“Rosa,” of course, is Nvidia’s next-generation CPU built on its Rigel core. It is due to launch in 2028 as part of the vendor’s upcoming Feynman datacenter platform.<br>Both Cadence and Synopsys are going hard into using agentic AI for their EDA and other chip design capabilities. Cadence in February announced AI Super Agent, an agentic tool for silicon design and verification, and in the following two months unveiled partnerships with Nvidia, TSMC, and Google around using AI agents for chip and system designs. Last month came the launch of AuraStack AI Super Agent (below) for front-end agentic workflow for automated chip design and verification.

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The AI Super Agents, at the direction of engineers, can simultaneously implement hundreds of simulation to do in less than a day work that now requires five weeks,...