[2504.09561] LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference

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arXiv:2504.09561 (cs)

[Submitted on 13 Apr 2025]

Title:LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference

Authors:Jianing Zheng, Gang Chen<br>View a PDF of the paper titled LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference, by Jianing Zheng and Gang Chen

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Abstract:In this paper, we propose LoopLynx, a scalable dataflow architecture for efficient LLM inference that optimizes FPGA usage through a hybrid spatial-temporal design. The design of LoopLynx incorporates a hybrid temporal-spatial architecture, where computationally intensive operators are implemented as large dataflow kernels. This achieves high throughput similar to spatial architecture, and organizing and reusing these kernels in a temporal way together enhances FPGA peak performance. Furthermore, to overcome the resource limitations of a single device, we provide a multi-FPGA distributed architecture that overlaps and hides all data transfers so that the distributed accelerators are fully utilized. By doing so, LoopLynx can be effectively scaled to multiple devices to further explore model parallelism for large-scale LLM inference. Evaluation of GPT-2 model demonstrates that LoopLynx can achieve comparable performance to state-of-the-art single FPGA-based accelerations. In addition, compared to Nvidia A100, our accelerator with a dual-FPGA configuration delivers a 2.52x speed-up in inference latency while consuming only 48.1% of the energy.

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Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2504.09561 [cs.AR]

(or<br>arXiv:2504.09561v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2504.09561

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arXiv-issued DOI via DataCite

Submission history<br>From: Jianing Zheng [view email]<br>[v1]<br>Sun, 13 Apr 2025 13:23:14 UTC (4,757 KB)

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