[2607.24221] DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

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arXiv:2607.24221 (cs)

[Submitted on 27 Jul 2026]

Title:DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

Authors:Rashid Aligholipour, Stefanos kaxiras, Yuan Yao<br>View a PDF of the paper titled DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation, by Rashid Aligholipour and 2 other authors

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Abstract:Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die) linked via high-bandwidth physical fabrics (PHY). As bandwidth and wiring density scale, however, these short-reach links are pushed closer to their signal-integrity limits, increasing susceptibility to noise, crosstalk, and channel loss, motivating stronger link-level reliability mechanisms such as forward error correction (FEC). Despite this trend, state-of-the-art simulation infrastructures often approximate inter-chiplet links using oversimplified, fixed-latency models. Such abstractions overlook the inherently dynamic, runtime-dependent behavior of the PHY -- including channel conditions (e.g., signal-to-noise ratio shifts, signal crosstalk, clock jitter), iterative decoder convergence and packet retransmissions, and application dynamics (e.g., LLC-misses that travel across chiplet boundaries) -- all of which are hard to determine offline. We show that neglecting these effects distorts inter-chiplet packet-level timing and high-level performance metrics such as IPC, leading to off-trend simulation results. We present DICE, an in-simulation, runtime PHY modeling in gem5 that captures the end-to-end inter-chiplet datapath, including QC-LDPC encoding/decoding, PAM4 modulation, lossy-channel transmission, LLR-based demodulation, adaptive packet re-sending, and PHY-level flow control between chiplets.

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Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2607.24221 [cs.AR]

(or<br>arXiv:2607.24221v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2607.24221

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Rashid Aligholipour PhD candidate [view email]<br>[v1]<br>Mon, 27 Jul 2026 09:53:10 UTC (7,912 KB)

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