Persistent State Machine: A Formal Computational Paradigm for High-Sparsity LLM Attention Acceleration [Version 7.0] | Zenodo
Skip to main
You are using an outdated browser. Please upgrade your browser to improve your experience.
Published July 30, 2026
| Version v7
Preprint
Open
Persistent State Machine: A Formal Computational Paradigm for High-Sparsity LLM Attention Acceleration [Version 7.0]
Authors/Creators
Esaka, Yusuke1
Show affiliations
1.
Cosmos Administrative Scrivener Office & Independent Researcher
Description
Persistent State Machines: Complete Mathematical Proofs and Vivado Implementation Synthesis (Version 7.0)
ABSTRACT:
We present a formal discrete framework for attention operators in Large Language Models (LLMs) via Persistent State Machines (PSMs). Computation is broadcast as instructions to stationary in-memory cells that evaluate local deterministic state transitions.
Complete mathematical proofs are provided for quantization error bounds, a concrete multi-phase discrete Softmax construction under an explicit bounded-logits assumption, deterministic finite-automaton (DFA) equivalence with spatial factorization into O(N) circuit size, and membership in DSPACE(O(n)).
A full two-phase engine—comprising local score evaluation and binary-tree reduction (including global max extraction and local exponential lookup)—was implemented in synthesizable RTL and processed through the AMD Vivado 2026.1 tool flow (logic synthesis, placement, routing, static timing analysis, and post-implementation power estimation) targeting the Zynq-7000 xc7z020 device.
After correcting a previous throughput exponent error in earlier drafts, the tool-estimated normalized dynamic energy of the synthesized logic is 0.0267 pJ/op under the stated operating conditions (Fmax = 283.8 MHz). Functional simulation with over one thousand random test vectors confirmed bit-exact agreement (zero discrepancy) with a fixed-point Python software reference.
Note: All reported energy and timing figures are tool estimates produced by the Vivado flow for synthesized logic; no physical FPGA board execution or silicon measurement was performed, and external system-level memory energy is excluded.
Japanese Patent Application No. 2026-177318 (Patent Pending)
Files
026_Zenodo_ASMA_Paper_v7_0_FullProofMaster.pdf
Files<br>(74.3 kB)
Name<br>Size
Download all
026_Zenodo_ASMA_Paper_v7_0_FullProofMaster.pdf
md5:eec884040073d8a06b69078645cb6d1b
74.3 kB
Preview
Download
1K
Views
35
Downloads
Show more details
All versions<br>This version
Views
Total views
1,056
Downloads
Total downloads
35
Data volume
Total data volume
1.4 MB<br>0 Bytes
More info on how stats are collected....
Versions
External resources
Indexed in
OpenAIRE
Communities
Details
DOI
DOI Badge
DOI
10.5281/zenodo.21694686
Markdown
[](https://doi.org/10.5281/zenodo.21694686)
reStructuredText
.. image:: https://zenodo.org/badge/DOI/10.5281/zenodo.21694686.svg<br>:target: https://doi.org/10.5281/zenodo.21694686
HTML
Image URL
https://zenodo.org/badge/DOI/10.5281/zenodo.21694686.svg
Target URL
https://doi.org/10.5281/zenodo.21694686
Resource type<br>Preprint
Publisher<br>Zenodo
Rights
License
Creative Commons Attribution 4.0 International
The Creative Commons Attribution license allows re-distribution and re-use of a licensed work on the condition that the creator is appropriately credited.
Read more
Citation
Export
Technical metadata
Created
July 30, 2026
Modified
July 30, 2026
Jump up
This site uses cookies. Find out more on how we use cookies
Accept all cookies<br>Accept only essential cookies