[2607.23402] Characterizing Warp Divergence from Pascal to Blackwell

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arXiv:2607.23402 (cs)

[Submitted on 26 Jul 2026]

Title:Characterizing Warp Divergence from Pascal to Blackwell

Authors:Alpin Dale<br>View a PDF of the paper titled Characterizing Warp Divergence from Pascal to Blackwell, by Alpin Dale

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Abstract:Since Volta introduced Independent Thread Scheduling (ITS), NVIDIA GPUs have been widely assumed to handle warp divergence in a fixed manner. We test this assumption across Ampere, Hopper, and datacenter and consumer Blackwell GPUs, using pre-ITS Pascal as a baseline. Combining cycle-accurate microbenchmarks, hardware counters, and static analysis of compiler-generated SASS, we separate stable behavior from architectural change. Across all tested generations, divergent paths serialize linearly with the number of paths $k$, following $T(k) \approx sk$ with no super-linear reconvergence penalty. Warp execution efficiency falls as $32/k$, the penalty is independent of occupancy, and predication removes the serialization cost. The same behavior appears on Pascal, showing that this programmer-visible cost model predates ITS. The compiler-emitted reconvergence machinery, however, has changed substantially. Pascal uses a per-warp SSY/SYNC instruction stack, whereas later generations use barrier-register instructions. Deferred reconvergence beyond the immediate post-dominator falls from 29 cases on Ampere to 2 on Blackwell. Blackwell also introduces a two-tier convergence-barrier classification, uniform-branch instructions, and explicit partial-mask warp synchronization, none of which appear on Ampere or Hopper. Controlled bit-flip experiments indicate that the new barrier class is a static compiler classification with no observable runtime effect in our tests. Thus, divergence retains a stable and predictable performance cost even as NVIDIA's control-flow ISA and reconvergence mechanisms continue to evolve.

Comments:<br>6 pages, 4 figures

Subjects:

Hardware Architecture (cs.AR); Performance (cs.PF)

ACM classes:<br>C.1.2; C.1.4; C.4; D.1.3

Cite as:<br>arXiv:2607.23402 [cs.AR]

(or<br>arXiv:2607.23402v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2607.23402

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Alpin Dale [view email]<br>[v1]<br>Sun, 26 Jul 2026 00:47:07 UTC (45 KB)

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