[2607.25504] At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference

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arXiv:2607.25504 (cs)

[Submitted on 28 Jul 2026]

Title:At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference

Authors:Bowen Wang, Chi Zhang, Diyou Shen, Renzo Andri, Navaneeth Kunhi Purayil, Luca Benini<br>View a PDF of the paper titled At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference, by Bowen Wang and 5 other authors

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Abstract:Fine-grained weight pruning and activation sparsification have emerged as effective approaches for reducing the compute and memory cost of inference for Transformer models. In the moderate-sparsity regime, Gustavson's dataflow provides a natural execution model for exploiting both activation and weight sparsity on vector processors through metadata-driven indexed accumulation. However, existing RVV architectures lack native support for this pattern, forcing kernels to rely on software index decoding and L1-backed indexed memory operations that keep sparse tensor contractions far below their roofline performance bound. We present Ventaglio, a runtime-configurable sparse execution unit coupled with RVV ISA extensions that drives sparse tensor contractions toward their roofline through indexed gather-accumulate-scatter support. Integrated into an open-source vector processing cluster and implemented in 12nm FinFET, Ventaglio accelerates sparse tensor contraction kernels by $6.9\text{--}7.4\times$ over optimized RVV baselines, with only $3.1\%$ area overhead for a cluster of tightly-L1 coupled vector processing elements. We build a performance-accurate instruction-level model of the Ventaglio extension, calibrate it against RTL implementation, and leverage it for scale-out performance analysis on a large $4\times4$ multi-cluster system. Using a DuoGPT-pruned LLaMA-3-8B model with practical $40\text{--}60\%$ dual sparsity, Ventaglio achieves $2.40\text{--}5.25\times$ and $2.06\text{--}3.16\times$ speedup over dense baselines during prefill and autoregressive decoding, respectively.

Comments:<br>5 pages, 4 figures, 34th IFIP/IEEE International Conference on Very Large Scale Integration SoC (VLSI-SoC 2026)

Subjects:

Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)

Cite as:<br>arXiv:2607.25504 [cs.AR]

(or<br>arXiv:2607.25504v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2607.25504

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Bowen Wang [view email]<br>[v1]<br>Tue, 28 Jul 2026 09:38:42 UTC (4,834 KB)

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