Looking inside a 1970s PROM chip that stores data in microscopic fuses
Looking inside a 1970s PROM chip that stores data in microscopic fuses
The MMI 5300 was a memory chip from the early 1970s, storing 1024 bits in tiny fuses.1<br>Unlike regular RAM chips, this was<br>a PROM (Programmable Read-Only Memory);<br>you programmed it once by blowing fuses and then it held that data permanently.<br>The chip I examined originally cost $70 and was built by MMI (Monolithic Memories Incorporated), a leading PROM manufacturer at the time.
The highly magnified photo below shows the chip's silicon die.<br>The metal layer on top of the silicon is most visible in this photo; the transistors and resistors fabricated from<br>silicon are underneath.<br>The wires around the edges are the 16 bond wires between the silicon die and the external pins.<br>In the upper left, the<br>1024 bits of data are stored in a 33×33 array of diodes and fuses.<br>(I'll explain the extra row and column below.)<br>This chip is built from NPN transistors, unlike the MOS transistors used in most modern chips.
Die of the MMI 5300 PROM chip, holding 1024 bits of information. Click image for a larger version.
To produce the die photo, I started with the chips below, in their 16-pin ceramic packages;<br>the 5300 and 6300 chips are essentially the same.2<br>Since the chips were in ceramic packages, I could decap the chip simply by knocking the metal lid off with a chisel,<br>revealing the silicon die.
The MMI 5300 and 6300 PROM chips are in ceramic packages. The chips have 1974 and 1973 date codes.
In the photo below, the silicon die is mounted very off-center in the package. It's unclear if that is intentional or sloppy manufacturing.<br>Tiny bond wires connect the die to the metal contacts of the package.
The MMI 5300 PROM with the lid removed, exposing the die.
Inside the chip
The diagram below shows the main parts of the chip, with the pins labeled.
The chip stores 1024 bits as 256 4-bit words.<br>The 8 address lines A0-A7 select one of the 256 words, and the bits are output on pins Out1-Out4.
The Program pin is used to store data in the chip by blowing fuses.<br>The Vcc and ground pins power the chip.
Die of the 5300 PROM with components labeled.
The 1024 bits of data are stored in a 33×33 array of diodes and fuses.<br>Note that the data array only takes up about a quarter of the chip; the rest of the chip holds the supporting circuitry.<br>Below the data array, address decode circuitry used the address lines to select one of 32 columns in the array.<br>To the right, DTL multiplexers4 reduced the 32 rows of output to the 4 desired outputs. The output drivers amplified these signals and sent them to the output pins.
The fuses
The chip stored data in tiny fuses. An intact fuse represented a 1, while a blown fuse represented a 0.<br>Thus, the chip was shipped containing all 1's, and the user programmed the chip by blowing fuses where a 0 bit was<br>required.<br>The fuses were fabricated from tiny regions of Nichrome metal that heat up and melt under high voltage.<br>(Nichrome is a nickel-chromium alloy that has much higher resistance than typical metals, causing it to heat up.<br>It is commonly used in applications such as toasters.)
A closeup of the fuses (purple) that store data. Inset circle shows a magnified fuse, showing the tiny horizontal crack indicating the fuse was blown.
The fuses are visible in the die photo above; they are the purple regions between the metal wiring.<br>The fuses are very small, about 8µm long.<br>I expected a blown fuse would vaporize entirely, but instead a blown fuse contains a tiny crack roughly 700 nm wide.<br>(This is the wavelength of red light, so the crack is just barely visible under the microscope.)
Address decoding
The PROM stored 1024 bits as 256 words of 4 bits. However, the bits are physically arranged in a 33×33 grid since<br>a square memory grid is more efficient than a highly-rectangular one.<br>To access the memory, address bits A3-A7 select one of the 32 columns.<br>The selected 32 bits in the column go through the multiplexers at the right, which select one bit out of each group of eight,<br>based on address bits A0-A2. The four selected bits become the four outputs.<br>Thus, addressing has two parts—one to select the column and one to select the four output bits—and they have separate circuitry,
Column selection uses 32 NAND gates,<br>implemented with multiple-emitter transistors.3<br>(The N and P silicon regions of the transistors are visible as rectangular boxes, with the brownish metal layer on<br>top connecting the regions together.)<br>Each NAND gate has a different combination of address bits A3-A7 either inverted or uninverted, so each address activates a different NAND gate, selecting the associated column.
You can see the binary counting in the emitters. The A7' and A7 lines alternate connections every column.<br>The A6'/A6 connections alternate every two columns, while A5'/A5 alternate every four, and so on.
Part of the column address decoder. Each...