GitHub - Midstall/claude-for-hardware: Claude Code skills for hardware design, validation, and bring-up · GitHub
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Midstall
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.claude-plugin
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evals
evals
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claude-for-hardware
Claude Code skills for hardware design, validation, and bring-up.
A plugin of focused skills that teach Claude how to do real hardware work:<br>designing reusable HDL, integrating an SoC, bringing up FPGAs and bare-metal<br>targets, building firmware boot chains, verifying designs against golden models,<br>validating codegen on real silicon, prepping a tapeout, and packaging EDA tools<br>in Nix. Each skill is domain-general but carries Midstall's house style:<br>failures should fail, fix the root cause, read the datasheet, test like it's<br>going to silicon, and write in ASD-STE100 Simplified Technical English.
Skills
Skill<br>Use when
hdl-module-design<br>Writing or refactoring an HDL module and you need it parameterized, validated, and testable
reference-driven-rohd<br>Implementing a block/protocol/peripheral in ROHD and you should fetch the spec, references, and reusable libs first instead of writing from memory
rohd-rtl-gotchas<br>Building or testing RTL in ROHD/rohd_bridge/rohd_hcl and hitting hierarchy, sim-setup, or SV-emission errors
soc-integration<br>Composing an SoC from peripherals and a bus, or generating device trees / ACPI from one description
rtl-area-timing<br>Optimizing RTL microarchitecture for area or Fmax when a design won't fit or meet timing
fpga-synthesis-fit<br>Synthesizing with yosys/nextpnr, fighting area/congestion, measuring Fmax, or instantiating block RAM
fpga-bringup<br>Loading a bitstream onto a real FPGA and driving it over JTAG/GPIO
bare-metal-bringup<br>Bringing up bare-metal or kernel code on a new arch/board that won't boot or hangs
firmware-boot-chain<br>Building or debugging a firmware/boot chain (SBI/UEFI/ACPI/bootloader) or measured boot
differential-verification<br>Verifying a DUT against a golden reference model with coverage-guided fuzzing
codegen-validation<br>Proving a compiler backend's output by executing it on a real CPU or fast emulator
tapeout-precheck<br>Prepping a design for tapeout: DRC/LVS signoff, submission packaging
nix-eda-packaging<br>Packaging EDA toolchains in Nix without dlopen/wrapper hacks
silicon-grade-discipline<br>Any silicon-bound code facing a fast-vs-correct tradeoff (the shared backbone)
Beyond skills
The plugin ships more than the skill files.
Agents (agents/) bundle the relevant skills into a focused reviewer you can<br>dispatch at the right moment:
rtl-reviewer reviews an HDL diff against the design and discipline red flags.
tapeout-signoff runs the precheck gate and refuses to wave real violations.
bringup-debugger drives the bring-up checkpoint ladder when hardware is dead.
Commands (commands/) are guided entry points that drive a workflow:
/fpga-fit runs the measure-don't-guess synthesis and timing loop.
/tapeout-check walks the tapeout signoff gate.
/hw-bringup drives the bring-up ladder for a stuck board.
Hooks (hooks/) enforce the house style mechanically: a write-time check<br>rejects em dashes, emoji, and malformed SKILL.md frontmatter, so the rules are<br>automated rather than repeated in prose. The same logic runs in CI via<br>scripts/lint-skills.sh.
Evals (evals/) are the benchmarks that prove the skills earn their keep:<br>usefulness (do they beat the unaided model), discovery (do they fire at the right<br>time), and adversarial discovery (do they resist bait and stay quiet on vague<br>prompts). See evals/README.md. These skills are measured, not<br>asserted.
Install
Add the...