Understanding the AXI Protocol: Applications and Functionality

The AXI protocol is powerful and easy-to-use for connecting modules within SoCs and FPGAs.

Intro to the AXI Protocol

AXI (Advanced eXtensible Interface) is an interface for connecting modules within an SoC or an FPGA. It is fully synchronous and can be as wide and as fast as needed to meet transfer requirements between modules. The strength of AXI is that it provides a robust means to control and verify that data has transferred, either single-strobe, burst, or streaming, while being easy to understand and implement.

AXI, more formally known as AXI4, is part of the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM, also known as the “Digital Highway from ARM”. AMBA also includes the Advanced Peripheral Bus (APB) and the Advanced High-Performance Bus (AHB) bus interface protocols. Together, they provide the protocols needed to implement an interconnected SoC containing a complex mixture of heterogenous processors and peripherals.

AXI and FPGAs

Within an FPGA, AXI4 is typically used to transfer data to and from memories using a memory-mapped architecture or from module to module using a streaming protocol without addressing.  There are two types of AXI4 used for memory-mapped transfers. AXI4-Full supports burst memory-mapped transfers such as used with DDR memories. These can be either reads or writes and they can be re-ordered by modules to maximize throughput. AXI4-Lite also supports memory-mapped reads and writes but it does not support bursts. It is normally used as a control interface to a peripheral that accesses control and status registers. AXI4-Stream is a unidirectional interconnect protocol that can either support single-strobe transfers, bursts, or continuously streaming data transfer. Its data is never re-ordered.

AXI is not a chip-to-chip interface. Its definition makes it very useful for module-to-module interconnect within an FPGA or SoC.  There are memory-mapped and streaming chip-to-chip interfaces that better manage the challenges of voltage levels and terminations and clock propagation, like SPI, Ethernet, DDR or PCIe. Additionally, most chip-to-chip interfaces are supported by IP modules within the FPGA or SoC that then have AXI ports for transferring the data to internal IP blocks.

Learn more about what AXI is in this blog post.

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AXI Protocol Benefits

The primary benefits of using modules with AXI connectivity are its availability, productivity and flexibility.

Availability

Many FPGAs are supported by an extensive library of IP blocks that can be interconnected using AXI. Often times these IP blocks are provided at no-cost when implemented within FPGAs and SoCs. Additionally, many other IP vendors provide modules that can be licensed and then easily implemented and interconnected using AXI ports. There are over 400 ARM partners offering IPs and tools that support the AXI interconnect ecosystem.

Productivity

Use of the AXI interconnect protocol provides a single interconnect standard across ALL domains and ALL partner IPs.  Therefore, there is only one standard to learn to perform these various interconnects. This increases productivity as time is not spent in design, implementation and simulation to create and verify dissimilar interconnect protocols. Significant time is often expended while validating, and iteratively fixing, modules with dissimilar interconnect protocols. Therefore, using the AXI interconnect protocol results in less time spent interconnecting IPs into a design and then validating robust operation.

Flexibility

Since the AXI interconnect protocol is not limited in speed or width, it provides the ability to configure the interconnect to meet and balance the system goals of performance, area, and power.  Also, having a consistent interconnect protocol by using AXI enables a seamless FPGA design.

Since AXI-Full and AXI-Lite are commonly used for accessing memory-mapped memories and peripherals, the data widths are normally implemented as a multiple of 8 to support byte-wide data. Bit widths of 32, 64, 128, or even 512 bits are common.  The AXI-Stream interface supports streaming data with a width of any number of bits and therefore is commonly used for DSP, video, and communication applications.

AXI Quality of Service (QoS)

AXI Quality of Service (QoS) is a feature that enables system designers to prioritize and manage data traffic within an SoC or FPGA. QoS settings in AXI interfaces allow different transactions to be assigned priority levels, ensuring that critical data transfers receive preferential treatment over lower-priority traffic. This is particularly useful in systems where multiple masters compete for access to shared resources, such as memory controllers or high-speed peripherals. By implementing QoS, designers can optimize bandwidth allocation, reduce latency for time-sensitive operations, and prevent...