RF Filter Design for ESP32-S3, Part 1: The Ideal Filter and First Layout

Sign in<br>Subscribe

Topology definition and electrical baseline without physical effects<br>"It requires a much higher degree of imagination to understand the electromagnetic field than to understand invisible angels. I speak of the E and B fields and wave my arms and you may imagine that I can see them, but I cannot really make a picture that is even nearly like the true waves."<br>— Richard Feynman, The Feynman Lectures on Physics, Vol. II (1964)<br>Problem<br>In early 2024, a hardware team reached out to Altiv Labs after their ESP32-S3 IoT product came back from fabrication with a filter response significantly worse than simulated. The matching degraded progressively from 2402 MHz toward 2480 MHz, a classic symptom of layout parasitics shifting the response. Two bench component swaps had produced partial improvement, but no systematic understanding of why. The question they brought was direct: how do we know, before the next board revision, what values will actually work?<br>Answering it required a model that included the electromagnetic behavior of the PCB layout, the real insertion effect of the RF switch, and the frequency-dependent behavior of the specific commercial components to be soldered, not ideal elements, not approximations.<br>Designing an RF filter for a Wi-Fi 2.4 GHz system looks straightforward on a schematic. The CLC PI topology is well understood, the target frequencies are fixed, and component values can be calculated analytically. The problem is that what meets the S1,1 target on screen rarely meets it on a board.<br>That model exists in CST Studio Suite. But the complete workflow to build it, ODB++ import from Altium, 3D model trimming, discrete port placement, EM co-simulation with the schematic environment, re-optimization against real Wi-Fi channel targets, and final conversion of ports to SPICE-based Lumped Elements using manufacturer models from Murata SimSurfing, is not documented in any consolidated, publicly available source. Fragments exist in official documentation and forum threads, but the operative connections between steps are absent.<br>This series closes that gap. It provides a reproducible, end-to-end methodology for RF engineers and researchers who need simulation predictions grounded in the same physics a VNA observes, before the board is built.<br>Introduction<br>Modern embedded RF systems typically operate across multiple signal paths simultaneously. A representative platform such as the ESP32, for instance, integrates Bluetooth, Wi-Fi, and often coexists with external RF front-end components, including switches and matching networks, all within a single compact design.<br>At the schematic level, designing an RF filter or matching network may initially appear straightforward. Component values can be calculated analytically, transfer functions look clean, and performance targets seem well within reach. However, this result exists purely in a mathematical domain, one that makes no concessions to physical reality.<br>Once the design is transferred to an actual PCB, a range of non-ideal effects begin to govern circuit behavior. Transmission lines introduce distributed phenomena, passive components exhibit parasitics and finite Q-factors, and the physical layout itself becomes an active part of the electromagnetic system, whether the designer accounts for it or not.<br>This is precisely where electromagnetic simulation becomes indispensable. Tools such as CST Studio Suite allow engineers to move beyond ideal assumptions and incrementally incorporate physical constraints into the design flow. By merging circuit-level simulation with full-wave electromagnetic analysis, they enable a controlled, progressive transition from schematic to manufacturable PCB.<br>This article presents a structured methodology for RF filter development, beginning with an ideal circuit topology, advancing through layout-aware simulation stages, and culminating in a model that accurately reflects real hardware behavior. At each step, additional physical effects and constraints are introduced, allowing the designer to understand not only how the circuit performs, but why it behaves the way it does.<br>RF architecture definition<br>The starting point for this workflow is the RF architecture recommended by Espressif for the ESP32-S3, taken directly from the hardware design guidelines. According to that reference, the RF circuit is composed of three main parts: the RF trace on the PCB, the chip matching circuit, and the antenna with its associated matching network. Espressif specifies that the RF trace should be controlled to 50 Ω, that the chip matching circuit must be placed close to the chip, and that a CLC structure is preferred for the chip-side network, used to adjust the impedance point and suppress harmonics.<br>Adopting this topology as the baseline rather than an arbitrary lumped network gives the design a stronger engineering foundation. The first schematic is not...