Closing the Hardware Gap: What QEMU 11.1 Brings to Arm Developers | Blog | LinaroClosing the Hardware Gap: What QEMU 11.1 Brings to Arm Developers | Blog | Linaro

Closing the Hardware Gap: What QEMU 11.1 Brings to Arm Developers<br>Alex Bennée

Tuesday, August 4, 202610 min read Please enter Mastodon Instance: Submit Cancel

QEMU

QEMU 11.1 demonstrates how emulation and virtualization can shorten the gap between architectural specification, hardware availability and production-ready software.

Introduction

New Arm architecture features often arrive before developers have broad access to production hardware. That creates a difficult gap for teams working on operating systems, firmware, hypervisors, toolchains and platform software: support must be developed and tested before suitable silicon is widely accessible.

QEMU helps close that gap by making emerging architectural features available through emulation and virtualization. The second of QEMU’s three planned releases for 2026, QEMU 11.1 expands that capability with support for FP8 arithmetic in Arm’s Scalable Vector Extension and Scalable Matrix Extension, experimental Generic Interrupt Controller version 5 emulation, more accurate modelling of wait-for-event instructions, and several additional improvements across the Arm ecosystem.

Testing FP8 Support for Arm AI Workloads

Smaller floating-point formats can help make increasingly large AI workloads more practical.

AI software developers increasingly need to support reduced-precision arithmetic, but validating that support can be difficult while compatible hardware remains scarce. Compiler developers, operating-system teams and runtime maintainers still need a way to exercise instruction handling, context switching and feature detection before systems using the newest architecture extensions are widely available.

One of the biggest updates to QEMU’s instruction emulation will be support for 8-bit floating-point (FP8) numbers for Arm’s Scalable Matrix Extension (SME) and Scalable Vector Extension (SVE) instruction sets. The implementation covers floating-point arithmetic, conversion, accumulation and scaling instructions, together with fused multiply-accumulate operations commonly used by modern AI inference workloads. Depending on the execution mode, these operations can be applied to vectors through SVE or matrices through SME.

Why use a format with less precision and numerical range than conventional floating point? Many AI workloads can tolerate reduced numerical precision without materially reducing the quality of their results. Smaller values reduce model size and memory-bandwidth requirements, while suitable hardware can perform more operations in parallel. The acceptable trade-off depends on the model and workload, and reduced-precision formats remain an active area of research, including proposed 4-bit and 2-bit formats.

QEMU’s role here is not to run production-scale AI models at competitive performance. It is to let developers validate the surrounding software stack: instruction decoding, architectural feature discovery, operating-system support, context management, exception handling and regression tests. This also makes it possible to add FP8 and SME coverage to continuous integration systems before compatible hardware is broadly available.

These new instructions are available automatically when running the `max` CPU type under Tiny Code Generator (TCG) emulation. Developers can also configure architectural properties such as the nominal SVE vector length to exercise different implementation assumptions.

Developers using Apple silicon M4 or newer systems can also run QEMU guests through Apple’s Hypervisor Framework (HVF), with SME exposed to the guest using support introduced in QEMU 11.0.

Reduced-precision arithmetic is only one example of software arriving alongside new hardware capabilities. Platform infrastructure must also evolve, particularly around interrupt delivery and virtualization.

GICv5

Interrupt-controller support is fundamental to operating-system bring-up and virtualization on Arm systems. The Generic Interrupt Controller (GIC) routes and manages interrupts across processors, devices and virtual machines, making it a critical part of both platform hardware and its supporting software stack. GICv4 evolved from the existing GICv3 design, both of which QEMU has supported through emulation and Kernel-based Virtual Machine (KVM) acceleration for several years. GICv5 is a more substantial redesign intended to address limitations identified in earlier generations.

With 11.1 we now have experimental support for emulation of this interrupt controller by specifying `-M virt,gic-version=x-5`. In QEMU, the x- prefix marks an experimental interface. Its behaviour and command-line syntax may change without following QEMU’s normal deprecation process.

Early emulation support gives firmware, Linux kernel and hypervisor developers a platform on which to begin implementation and...