TensorLift: Auto Extraction of ISA Semantics from Accelerator RTL via MLIR

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[2604.13523] TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting

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Computer Science > Hardware Architecture

arXiv:2604.13523 (cs)

[Submitted on 15 Apr 2026 (v1), last revised 12 Jul 2026 (this version, v2)]

Title:TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting

Authors:Ruijie Gao, Haoran Jin, Jirong Yang, Nathaniel Bleier<br>View a PDF of the paper titled TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting, by Ruijie Gao and 3 other authors

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Abstract:Numerous tensor accelerator designs have been proposed, yet most lack well-documented ISAs and compiler backends, limiting evaluation to a handful of operators. Recent work has shown that given a tensor-level ISA specification, complete software stacks including compiler backends can be automatically generated--but writing such specifications remains a manual, expert-driven process.

We present ATLAAS, the first end-to-end MLIR-based pipeline that lifts RTL-extracted accelerator semantics to tensor ISA specifications. Starting from bit-level LLVM IR produced by prior architecture-level model extraction, ATLAAS applies an 8-pass semantic lifting pipeline that progressively recovers high-level tensor structure--MAC idioms, saturation semantics, multi-dimensional buffer organizations, and data layout transformations--emitting specifications that immediately enable automatic software stack generation through the ACT ecosystem.

We evaluate ATLAAS on the Gemmini systolic-array accelerator, where the pipeline collapses bit-level MLIR by up to 92.9% on processing elements and 24-34% on controller modules. ATLAAS discovers hardware features omitted from the hand-written reference, with correctness validated via Z3 SMT equivalence proofs. Generality is confirmed on TVM's VTA processor, where the same pipeline lifts all four datapath modules without accelerator-specific changes, enabling an automated path from RTL to a performance-competitive compiler backend.

Comments:<br>Accepted by ICCAD '26, this is not the camera-ready version

Subjects:

Hardware Architecture (cs.AR)

Cite as:<br>arXiv:2604.13523 [cs.AR]

(or<br>arXiv:2604.13523v2 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2604.13523

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arXiv-issued DOI via DataCite

Submission history<br>From: Ruijie Gao [view email]<br>[v1]<br>Wed, 15 Apr 2026 06:15:56 UTC (1,502 KB)

[v2]<br>Sun, 12 Jul 2026 19:35:34 UTC (1,897 KB)

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View a PDF of the paper titled TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting, by Ruijie Gao and 3 other authors<br>View PDF<br>HTML (experimental)<br>TeX Source

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