[2608.06791] HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation

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arXiv:2608.06791 (cs)

[Submitted on 7 Aug 2026]

Title:HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation

Authors:Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura, Le Chen, Venkatram Vishwanath, Zhenman Fang, Caiwen Ding<br>View a PDF of the paper titled HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation, by Yuebo Luo and 6 other authors

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Abstract:Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort. Even with high-level synthesis (HLS), designers still need extensive hardware expertise to build high-performance accelerators. Although large language models (LLMs) have demonstrated strong software-generation capabilities, even frontier models lack the hardware intuition and procedural knowledge needed to reliably translate baseline C/C++ programs into high-performance HLS designs: they struggle to identify effective architectures, follow the optimization processes used by HLS experts, and apply hardware transformations consistently across diverse kernels. We present HLSmith, an expert-guided framework for translating C/C++ programs into optimized HLS accelerators. HLSmith combines three components: an HLS optimization expertise library that encodes guarded transformation recipes, their applicability and prerequisite conditions, and unsafe cases to avoid; a staged, feedback-driven orchestration flow modeled on expert HLS development practice that guides agents through synthesis, bottleneck analysis, and optimization; and a tool-grounded model-adaptation pipeline that converts optimization trajectories from commercial frontier models into training data for fine-tuning open-weight LLMs. We evaluate HLSmith on PolyBench against ChatHLS, a leading prior agent-orchestration framework for HLS accelerator development. HLSmith achieves a geometric mean speedup of 4.24x over ChatHLS while producing functionally correct designs, in both software and RTL simulation, for every benchmark, compared with ChatHLS's 57% valid-design rate. It further reaches speedups of up to 252x and 138x with commercial frontier models and open-weight models, respectively.

Subjects:

Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)

Cite as:<br>arXiv:2608.06791 [cs.AR]

(or<br>arXiv:2608.06791v1 [cs.AR] for this version)

https://doi.org/10.48550/arXiv.2608.06791

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arXiv-issued DOI via DataCite (pending registration)

Submission history<br>From: Yuebo Luo [view email]<br>[v1]<br>Fri, 7 Aug 2026 04:27:04 UTC (12,291 KB)

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