Talking with Synopsys about the Physics of Chip Design at DAC 2026
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Talking with Synopsys about the Physics of Chip Design at DAC 2026
George Cozma<br>Aug 11, 2026
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Hello you fine Internet folks,
I did an audio interview with Ravi Subramanian from Synopsys where we talked about the physics that goes into chip design and EDA tools.
Ravi Subramanian<br>Hope y’all enjoy!
The transcript below has been edited for conciseness and readability.<br>George Cozma: At AMD’s Advancing AI was last week, you guys made some announcements there about 3DIC, and I would just like to learn a little bit more about that and hear a bit more about how you guys are thinking about thermals, but not just thermals, things like current such how to carry current from package to the compute dies?<br>Ravi Subramanian: So maybe a good starting point is the two main trends going on in computing from a pure silicon perspective, chips are getting bigger and bigger to the point where we have some reticle-limited chips. So we see that companies are using 2.5D and 3D types of integration techniques to have multi-die solutions to handle the ever-increasing compute complexity.<br>Thermals have always been a problem in chip design, so it’s not new. The first wave of big thermal innovation really had to do with the early eras of CPUs. As CPUs were getting faster and faster, how did they need to allow the device to operate in a package that’s sitting inside a laptop or sitting inside a desktop. Then came the mobile communications world brought some severe limits, because it was the first time the whole chip operation was determined by a battery-powered device.<br>George Cozma: Holds up phone.<br>Ravi Subramanian: Bingo. Exactly. All of a sudden, what was needed in doing low-power design, in terms of the EDA tools to do low-power design, and what was needed in terms of managing thermal effects not just from the compute die, but also from the power amplifier, which is sitting not so far away from the compute die in that chip, and then the battery, which is also creating heat. So all of a sudden, we now have a system where it’s not so simple to put a fan in a chassis and control things. The mobile industry really created the first step-function in how you need to think about thermal from a system perspective.<br>Then fast-forward, we go to automotive chips, and then we see regulations or rules really determining how the chip should operate because of the environment that it’s in.<br>George Cozma: So for automotive, is it less the actual thermals of the chip and more the environment of where the chip is being placed?<br>Ravi Subramanian: So the environment is a bigger factor, but if you look at a typical mobile SoC, it’s about 2 to 2.5 billion gates. A typical automotive ECU chip now is about 7 billion gates. So it is bigger, 3x bigger, and there are big power challenges. As a simple example, the way that’s really measured now is, “Oh, it translates into a much smaller range for the car,” because of how much energy is consumed by the compute die. So Mercedes, BMW, the US car makers, and others have talked about what’s the range restriction because of how much [power] is consumed by the chip.<br>Then we get to the data center, which is now another type of system with another set of constraints around the chip, the package, the rack, and then the whole building that everything is sitting in. So that’s the scale of how the thermal problem has changed, right? With different system complexity and the importance of not only the chip power dissipation and the way packaging is handled, but also the environment and what the environment brings in.<br>So now, if we look at 3D-IC and chip-in-package, and maybe more specifically about AMD…<br>George Cozma: If I remember correctly, AMD announced at their Advancing AI event which was last week and while there Synopsys announced the release of 3DIC which came with AMD as the co-partner for it.<br>Ravi Subramanian: Yes, yes. So AMD has been a leader since their presentation at ISSCC, I believe it was in 2019, when they disaggregated the die, and then they showed what the advantage is. That was the first seminal paper in this field that really set the stage for what’s the thinking behind going multi-die, and obviously evolving that to 2.5D and 3D.<br>Now, the minute you go multi-die, you get a number of advantages in terms of the total cost of the solution because of the fact that you’ve really thought about which logic node should which processing be in. But then what you’ve also done is you created a problem in that you have to move so much data around, and the energy consumed by moving the data.<br>So to get higher performance, Moore’s Law only gave you so much. You pick an advanced node, you can get the highest performance there, but then within a package now, you have multiple dies, each one having power dissipation during operation, which is very much related to the workload running on it.<br>So the first step is...