RF Filter Design for ESP32-S3, Part 2: PCB Effects and EM Co-Simulation

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This is Part 2 of a three-part series on ESP32-S3 RF filter design.<br>Inclusion of PCB physical effects and intermediate validation<br>"This velocity is so nearly that of light, that it seems we have strong reason to conclude that light itself is an electromagnetic disturbance in the form of waves propagated through the electromagnetic field according to electromagnetic laws."<br>— James Clerk Maxwell, Lecture at King's College, London (1862)<br>Introduction<br>The first stage of this workflow established a clean electrical baseline: an ideal CLC filter, optimized in the schematic domain, transferred to Altium as a first PCB implementation. At that stage, the circuit existed in two parallel representations, a mathematically refined schematic in CST and a physical layout in Altium, but these two representations had never been connected. The simulation had no knowledge of the board.<br>This second stage closes that gap. By exporting the PCB layout from Altium and importing it directly into CST Studio Suite, the physical structure of the board becomes part of the electromagnetic model. The routing geometry, pad shapes, copper transitions, and dielectric stack all begin to influence the simulated response. The filter is still built from ideal lumped components, but the environment in which those components operate is no longer ideal.<br>The result is a co-simulation: the circuit elements are evaluated together with the electromagnetic behavior of the layout, producing a response that reflects not just the component values but also the parasitic effects introduced by the PCB itself. This is the first stage at which the simulation can reveal problems that no schematic-level analysis can detect, frequency shifts, impedance distortions, and coupling paths that exist only because of physical geometry.<br>This article documents that transition, from the export of the Altium layout to the re-optimization of component values under layout-aware conditions, and closes with a direct comparison against the Stage 1 baseline.<br>Export from Altium<br>The first step is to generate the ODB++ output from the Altium Designer project. ODB++ is a manufacturing exchange format that captures the complete PCB structure, layer stackup, copper geometry, pad definitions, drill data, and component placement, in a form that CST Studio Suite can interpret directly as a three-dimensional electromagnetic model.<br>In Altium Designer, go to File → Fabrication Outputs → ODB++ Files . In the output configuration dialog, verify that all signal layers, the board outline, and the component placement data are included in the export. Confirm the stackup parameters are correctly defined, layer thicknesses, dielectric constants, and copper weights, since these values will directly determine how CST constructs the 3D model.<br>Don’t forget to check “Used On” to plot all used layers.<br>Generate the output and confirm that the ODB++ package has been created without errors before proceeding to the import step. All files will be present at the Project Outputs folder.<br>Import into CST Studio Suite<br>With the ODB++ file available, the next step is to load the PCB layout into CST Studio Suite as a three-dimensional structure.<br>Load the 3D layout<br>In CST, go to Modeling → Import/Export → 2D/EDA Files → ODB++ and select the exported package.<br>CST will parse the file and reconstruct the board geometry, including all copper layers, dielectric substrates, and component footprints, as a full 3D model. Review the imported structure carefully to confirm that the layer stack, copper features, and board outline match the original Altium design.<br>You have now successfully imported the board from Altium.<br>3D Model Trimming<br>The imported model represents the complete ESP32-S3 PCB, which is far larger than the region relevant to the filter simulation. Working with the full board geometry at this stage is unnecessary and would increase simulation time and RAM usage without adding meaningful information to the filter analysis. The model must therefore be trimmed to isolate only the region of interest before any further setup is performed.<br>Region of interest.<br>In the CST 3D editor, use the geometry cutting tools to remove all areas of the board outside the filter region. The area to retain is the CLC network itself, components CRF1, R0L, and CRF2, together with their immediate copper connections: the RF trace entering the filter from the ESP32-S3 RF port, the trace exiting toward the antenna matching network, and the ground return paths directly associated with the shunt capacitor pads. Copper and dielectric geometry beyond this boundary does not contribute meaningfully to the filter response and should be excluded.<br>Delete the top and bottom solders.<br>Press “P” to select points around and below the desired geometry.<br>Click on Modeling - Shapes - Brick, press ESC to automatically select the points.<br>In the Brick dialog box, select...