fearless_simd v0.7: 64-bit integers, improved generics, SSE2, and upcoming v1.0 - Linebender

fearless_simd v0.7: 64-bit integers, improved generics, SSE2, and upcoming v1.0

Shnatsel, August 12, 2026

fearless_simd takes unsafe out of SIMD.

No matter what level of abstraction you're after, be it autovectorization and multiversioning, portable SIMD, or safe access to raw intrinsics and nothing more, fearless_simd has you covered!

It features zero dependencies, short build times, safe public APIs, and very little unsafe under the hood - orders of magnitude less than the alternatives!

The major additions in v0.7 are support for 64-bit integers, an explicit SSE2 level replacing scalar fallback on x86, improved support for generic programming, and more implemented SIMD operations.

This is also the last major release prior to Fearless SIMD v1.0, if no concerns about the API are raised.

64-bit integers

The entire API surface of fearless_simd is now also exposed for u64 and i64 vector types.

Earlier releases didn't support 64-bit integer vectors due to hardware support being spotty. For example, AVX2 lacks hardware support for many operations on 64-bit integers, so it would require emulating those operations using the available SIMD instructions to get decent performance.

Keeping track of which intrinsics are part of which instruction set was also challenging, and getting it wrong would be a memory safety violation. However, in v0.5 we made the compiler keep track of it for us, which removed the vast majority of unsafe blocks from fearless_simd and made implementing operations with uneven hardware support much easier.

All the other integer vector types (i8,u8,i16,u16,i32,u32) and f32/f64 were already supported by previous releases, so 64-bit integers were the last missing piece for full type coverage. We will investigate supporting f16 once the type is stabilized in the standard library.

More operations

swizzle_dyn is now implemented for all widths to allow arbitrary byte shuffles. I've also contributed performance improvements for this operation to std::simd. Unlike std::simd, Fearless SIMD supports both zeroing out-of-bounds indices and returning implementation-defined (but memory-safe) results for when you're sure all indices are in bounds, which is cheaper than zeroing on some platforms.

All types can now be widened/narrowed; e.g. you can convert vectors of u8 to u16, or u16 to u8 in SIMD code. You get to choose whether narrowing conversions wrap, like the as operator, or saturate, or do the cheapest thing the platform has to offer (useful if you're sure the values fit into the narrower type).

Added convenience functions shift_elements_left, shift_elements_right, rotate_elements_left, and rotate_elements_right for better compatibility with the std::simd API. They could already be implemented in terms of slide, but this makes the intent more clear.

Improved generic programming

Support for generic programming - writing functions that are generic over the vector type - has been substantially improved. Here are just a few highlights:

The SimdBase trait now abstracts over both integer and float vectors, and implements all methods available on both integers and floats.

Improvements to the Bytes trait allow generic bitcasts (safe transmutes) between SIMD vectors.

Every single operation on SIMD types is now available through a trait. There are no remaining operations implemented only for concrete types.

Associated types such as SimdBase::Element and SimdBase::Array now encode a lot of generic bounds to allow generic operations on them.

See the full changelog for details. All in all, generic SIMD programming is now much more pleasant, and allows expressing more algorithms generically.

These improvements also benefit users who abstract over SIMD vector types using macros, writing e.g. $type::from_slice instead of T::from_slice. They no longer need additional crates such as paste to inject types into function names, since all operations are now available on the types themselves.

Explicit SSE2 support

These days x86 systems without SSE4.2 are very rare. However, since SSE2 is part of the baseline instruction set in both x86_64 and i686 Rust targets, the presence of SSE2 can be assumed, without any runtime dispatch or multiversioning. Certain crates only need a very limited set of vector instructions and don't benefit from later extensions, so forgoing runtime dispatch can simplify the code and reduce binary size.

To better serve this use case, Fearless SIMD now has an explicit Sse2 level with operations expressed in terms of SIMD intrinsics, rather than relying on autovectorization of the Fallback level when SSE4.2 is not available. This improves performance on x86 when the user opts out of selecting the best SIMD implementation at runtime.

SSE2 remains a runtime-detected level on the tier-2 i586 targets, and can be disabled there using the usual multiversioning controls.

Build time...