A NASA processor now being tested at JPL is performing 500 times faster than the radiation-hardened chips currently used in spaceflight — yet fits in the palm of a hand and could let future spacecraft make AI-powered decisions on their own when communicating with Earth can take 44 minutes round-trip.

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A palm-sized processor undergoing tests at NASA’s Jet Propulsion Laboratory has produced an early result that could reset expectations for computing in space. JPL says the High Performance Spaceflight Computing processor, known as HPSC, is showing indications of 500 times the performance of radiation-hardened processors currently used in spacecraft.

The comparison comes from an active test programme, not a flight mission. JPL reported in May that engineers were putting the new silicon through functional, radiation, thermal and shock testing. It has not yet completed spaceflight qualification, and NASA has not named the first mission that will carry it.

Those boundaries matter, but so does the scale of the result. A processor with that much additional headroom could analyse complex sensor data and run tightly defined artificial intelligence aboard a spacecraft. Near the widest separation between Earth and Mars, when a round trip for a radio signal takes roughly 44 minutes, local decisions are not merely convenient. Some are unavoidable.

The 500-times result is bigger than the design target

NASA began the HPSC programme with a goal of delivering at least 100 times the computing capability of current spaceflight computers. The 500-times figure is an early indication from tests of the manufactured processor. It does not mean every program will finish 500 times sooner, since real performance varies with the task, software, memory traffic, available power and how a complete flight computer is configured.

The distinction also explains why both figures appear in NASA material. The 100-times number describes the programme’s broad capability target. The 500-times number reports what the first hardware is indicating relative to radiation-hardened chips now in use. JPL began testing in February 2026 after the processor sent its first “Hello Universe” message, and NASA’s current programme page still places the device in the test and qualification phase.

Qualification is the decisive hurdle. A fast chip that produces errors after a radiation strike, fails during launch vibration or overheats inside a spacecraft is not useful. NASA and Microchip Technology designed HPSC to combine a large performance increase with fault tolerance, error correction and controls that let missions trade computing speed against electrical power.

Space processors trade speed for survival

Spacecraft computers often look generations behind terrestrial processors because reliability takes precedence over headline speed. Energetic particles can flip stored bits, disrupt a running calculation or trigger more serious faults. Hardware may also face vacuum, wide temperature swings and years of operation beyond the reach of a repair technician.

Existing radiation-hardened devices show that trade-off. BAE Systems’ RAD750 specification, for example, lists performance above 400 million instructions per second at 200 megahertz while emphasising radiation tolerance and a record of use across major missions. NASA has not said that the RAD750 alone is the specific basis for its 500-times comparison, so the claim should be understood as a comparison with the broader class of flight processors now operating.

HPSC attempts to keep that resilience while adopting a much more modern architecture. Microchip’s commercial version is called PIC64-HPSC. Its published design includes eight 64-bit RISC-V CPU cores, vector extensions for accelerated mathematical work, networking and specialised functions for machine-learning workloads. Microchip rates its AI arithmetic at up to two trillion operations per second for eight-bit integer calculations, though an actual mission’s throughput will depend on its implementation.

The chip fits in a hand, but the computer will be larger

NASA’s photographs accurately show a system-on-chip small enough to sit in a gloved palm. “System-on-chip” means that the device integrates central processors and several supporting functions onto one piece of silicon. It does not mean the photographed component is a complete flight computer.

A usable spacecraft computer still needs a circuit board, external memory, power regulation, connectors and interfaces to instruments and other vehicle systems. Designers may also add shielding or redundant equipment. The palm-sized comparison is useful for conveying how much computing is concentrated in the component, but it should not be read as the final size or mass of an operational unit.

That integration can still simplify spacecraft designs. It can also make it practical to process data close to the instrument that generated it, reducing delays...