RISC-V: What Matters

RISC-V : What Really Matters - by Babbage - The Chip Letter

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RISC-V : What Really Matters

Babbage Aug 16, 2026

Readers may have seen the recent blog post from Dmitri Grinberg RISC-V: They Should Have Known Better which sets out, at some length, his criticisms of the RISC-V architecture. Here’s a sample: Now, about those compressed instructions. Let us look at them in detail. They are hilariously poorly designed. Say you want to store a byte to a register plus offset. What range of offsets can a 16-bit instruction encode? Zero through three. Not thirty three, not three hundred and three. Three! Well, maybe it is better for storing a halfword? Nope... zero or two. What even? Why?

It’s fair to say that I would normally be put off by the slight tone of disdain that runs through most of the post, but to be fair Grinberg does go into a lot of detail with his complaints and the tone of some of the early RISC-V papers was quite, well, combative in its criticisms of other architectures. Incidentally, Grinberg is the author of many interesting projects including one of my favourites Linux/4004 - Slowly booting full Linux on the intel 4004 for fun, art, and absolutely no profit (yes you read that correctly!) which is very fun indeed.

There is an extensive (250+ comment) Hacker News thread on this post and two of the top voted comments neatly capture my response. The first is from Luke Wren who designed the open source Hazard3 RISC-V core used in the Raspberry PI Pico 2: RISC-V is... fine. It satisfies my two requirements for an ISA as a hobby CPU designer, which are: 1. Supported in mainline LLVM and GCC. 2. I can implement it without lawyers sending me a love letter. Everything else, I can fix in post. There are enough good ideas spread across the extensions that I can assemble a reasonably put-together, curated embedded ISA with competitive performance and code density that admits a simple implementation.

The second from a member of Meta’s MTIA accelerator team: We are using RISC-V for AI accelerators to great success https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billio... RISC-V was a great choice due to being so customizable and extensible.

That’s pretty much all that matters. We can debate the technical merits or other of the RISC-V ISA endlessly. Any ISA inevitably has flaws but RISC-V is free, well supported and extensible. These factors alone will ensure its success. RISC-V ultimate position in the high performance application - e.g. desktop and smartphone - market is still debatable though. On this issue Grinberg’s article says: The second category for big-compute is actual desktops and SBCs that do interactive computation, browsing, gaming, and other such "desktop work". I do not expect RISC-V to be a serious player at the top of this market. Simply put, the architecture is not designed for it, as pointed out above. Additionally, this market has the margins to afford licensing a much-better-designed aarch64 core from ARM, and gain proper support from a much larger corpus of software. Before you get your megaphone to shout about "openness", please note that the openness of the RISC-V spec is not relevant here at all, because an open spec does not magically materialize a well-designed out-of-order core for you for free.

It’s obviously true that you don’t get a big core for free with an Open ISA but openness is still relevant. RISC-V enables firms with talented CPU designers to work to build high performance designs without having to get permission - probably denied in many cases - from Arm. We’ve seen this from firms such as Tenstorrent, Rivos, SiFive and many more. Where I do agree with Grinberg is that many firms will prefer to pay the margin needed to license and gain access to the support and roadmap that comes with Arm’s aarch64. In many cases the unit economics will make developing your own core a bad idea and a licensable RISC-V core with the appropriate performance may not be available. There is a whole other debate to be had about whether a true arm competitor using arm’s business model, but based, on RISC-V will emerge. I have my doubts. Plus in 2026, with so much focus on the development of dedicated machine learning accelerators, won’t most firms want to apply their resources and scarce talent where they can really distinguish themselves from competitors? That probably isn’t building a high-performance RISC-V core from scratch unless its part of an accelerator.

Three years ago we ran a poll to gather readers views on the outlook for RISC-V, so I thought it would be interesting to run it again. When the results are in we’ll see how things have changed.

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