RVA23 vs ARMv9 a Small Experiment · GitHub

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camel-cdr/rv-vs-arm-chibicc.md

Created<br>March 4, 2025 21:43

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RVA23 vs ARMv9 a Small Experiment

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rv-vs-arm-chibicc.md

RVA23 vs ARMv9 a Small Experiment

I was curious to see how RISC-V and ARM compare in terms of dynamic instruction count and code density, so I devised a small experiment to compare the ISAs.

As a test codebase, I choose the chibicc C compiler, because it's a medium size project and is quite easy to compile.<br>To benchmark chibicc I just used it to compile itself, which should be a quite realistic workload to simulate a complex non-regular application.<br>I merged all files into one and did some minor modifications, the code can be found at: https://godbolt.org/z/xr3nEW8Wf

You may notice that I added unoptimized scalar implementations of the mem* and str* functions from musl-libc.<br>This is because I decided to not include SIMD code in this experiment, in an effort to remove more unknown variables and focus on comparing the base ISAs.<br>Without these measures, the results seemed similar.

Without further ado, below is the table comparing the results:

staticQEMUGEM5<br>ISACompilerBytesBytesInsnsuops**Sim-TimeInsnsuops

RVA22 clang-19 772K 1221M 424M +0M = 424M 0.221s 438M +0M = 438M<br>RVA22 gcc-15 772K 1309M 445M +0M = 445M 0.217s 459M +0M = 459M<br>RVA23* clang-19 772K 1185M 423M +0M = 423M 0.243s 438M +0M = 438M<br>RVA23* gcc-15 772K 1265M 441M +0M = 441M 0.217s 456M +0M = 456M<br>armv9* clang-19 944K 1543M 386M +39M = 424M 0.225s 399M +70M = 469M<br>armv9* gcc-15 936K 1688M 422M +39M = 460M 0.236s 435M +66M = 501M

*excluding SIMD/vector instructions

**Derived from the "Apple Silicon CPU Optimization Guide": ((ld|st)\w.*#\w*(\]!)*$)|ldp|stp, so load/store pairs and pre-/post-index load/stores

As mentioned before, I'm explicitly excluding SIMD from this experiment, so I used the following compiler arguments to achieve this:

RVA22: -O3 -march=rv64gcb -static

RVA23: -O3 -march=rv64gcb_zcb_zfa_zicond -static

armv9: -O3 -march=armv9-a+nosimd+nosve -static

Let's go through the results from left to right.

Firstly, the static sizes of the RISC-V binaries is about 18% smaller than the sizes of the ARM ones.<br>The sizes are extremely similar for both RVA22 and RVA23, and regardless of compiler.<br>For the dynamic instruction size however, that is the sum of executed-instructions-lengths, there is a clear improvement going from RVA22 to RVA23.<br>RVA22 needs to fetch 21% fewer bytes than armv9 and RVA23 goes down to 24% fewer bytes than armv9.<br>AFAIK QEMU doesn't come with the ability to count the executed-instruction-lengths out of the box, so I needed to patched the tcg/plugins/insn.c plugin.

When it comes to dynamic instruction count, ARM ends up the clear winner with on average of 6.5% fewer instructions that need to be decoded.<br>But the instructions them self isn't what ends up executing in the backend.<br>Due to the more complex...